on IMX7D RMII inteface, how to configure PHY 50MHZ reference clock as input

[hyoungkikim]

hi experts 

on my custom board  using imx7d , i like to connect network phy as RMII mode 

a phy ic  clocks out 50MHZ referece clock , so i connected this clock to ENET1_TX_CLK pin

on datasheet  IOMUXC_GPR_GPR1 register has ENET1_CLK_DIR and ENET1_CLK_SEL bits

could i set these register bits by device tree  or do i have to code in kernel ?

thank you in advance 

sincerely

[Zhiming_Liu]

Please refer this function to configure GPR1 register, the code need to modify to set bits you need.

#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
	int ret;

	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
		(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);

	ret = set_clk_enet(ENET_125MHZ);
	if (ret)
		return ret;

	return 0;
}