Dear Joseph
Thank you for your reply.
clk_disable_unprepare(lcdifv3->clk_pix);
clk_set_rate(lcdifv3->clk_pix, vmode->pixelclock);
clk_prepare_enable(lcdifv3->clk_pix);
my code is using lcdif version code , so added debug log in lcdif function lcdif_crtc_mode_valid() (drivers/gpu/drm/imx/lcdif/lcdif-crtc.c) to check if vmode->pixelclock i.e ~70 mhz is set in clk_set_rate(). Exact clock rate of 69.3 mhz is retrieved in lcdif_crtc_mode_valid() function.
>>And also that the specified speed is covered in SW for the selected PLL.
can you please provide bit more details about it? as per my idea, pixel clock in jd9365da driver code is set to ~70 Mhz according to display parameters (800 *1280) and dsim->bit_clk is calculated in sec_mipi_dsim_check_pll_out(drivers/gpu/drm/bridge/sec-dsim.c) is ~420 Mhz . is PLL different from dsim->bit_clk?
Attached latest bootlog for reference.
Rgds
kot