I only get the information about the SDRAM connections from Karo, but I believe this could help. The memory space is constructed with four chips, whereby two chip selects are used. So I did some further investigations on the code and the strange behaviour if using the two chip select configuration in flash_header.S.
I don't know exactly if the following issues are related to the TX53-8020 as well, you are using. I don't if you have als 1GByte DDR3 memory, can't find any information on that in the www. But maybe you should have a look on it.
# Two chip selects are used. In this case 512MByte are controlled by one chip select. The configuration of the MMU was wrong, as the original patches assumes 1GByte on ONE SINGLE chip select. The chip arrangement is equal to the MX53 Loco board (i.MX53 QSB), so in board_mmu_init() (tx53.c) the following changes must be done:
- X_ARM_MMU_SECTION(0x700, 0x700, 0x400, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0x700, 0xB00, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
+ X_ARM_MMU_SECTION(0x700, 0x700, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */
+ X_ARM_MMU_SECTION(0x700, 0x900, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */
+ X_ARM_MMU_SECTION(0xB00, 0xB00, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD1 512M */
+ X_ARM_MMU_SECTION(0xB00, 0xD00, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD1 512M */
# dram_init() in tx53.c must use both SDRAM banks.
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if defined(PHYS_SDRAM_2)
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
return 0;
}
# The configuration in tx53.h must slightly be changed to support two SDRAM banks.
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
#define iomem_valid_addr(addr, size) \
((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \
|| (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
# Change CONFIG_MX53_EVK to CONFIG_MX53_LOCO in tx53.h otherwise the two SDRAM banks are not supported in mmu.h
# PHYS_SDRAM_1_SIZE in flash_jeader.S should be the complete SDRAM size not only the size of one ship. During configuration it will be checked, if two SDRAM banks should be used. This is the case if the memory space is larger than SZ_512M. So in this case it would be better to do the following.
#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
Unfortunately I can't test these changes right now, my NAND flash gots corrupted yesterday and flashing with the Advanced Toolkit fails with "Too many bad blocks encountered" :-(