modifying the SNVS LPCR register effects the edma

[Jonny_T]

We are currently developing on the imx 7ulpevk and have an issue where reading / modifying the SNVS LPCR register, in this instance to update RTC, while performing a high-speed I2S receive operation using the EDMA peripheral to memory results in a FIFO overflow for the I2S FIFO.

We don't have the issue when reading / modifying the SNVS HPCR register.

Is the SNVS LPCR register only supposed to be read / write on MCU boot or suspend?

If so, why does the demo SRTM code try to update the SNVS LPCR under normal operation?

Why does reading / writing the SNVS LPCR register result in a FIFO overflow in a seemly unrelated part of the MCU?

[Zhiming_Liu]

1.The LP register can be read and written during locks and privilege modes.

2.User needs to setup access permissions in XRDC setting.Also, user needs to make sure that both cores should avoid access confliction, that is, both cores should not access the same module at the same time.

3.SRTM also meet the above conditions

Can you check if your operation meet these conditions?