Hi,
Due to hardware limitations, the usdhc clock is constrainted to be 132MHz.
&usdhc1 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <132000000>;
};
&usdhc2 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <132000000>;
};
The clock speed's max value can't exceed 150MHz.
[note]
1. For High speed mode, uSDHC IO voltage must be 1.8V.
2. if you are using 3.3V IO, The max value of uSDHC clock speed can't exceed 50MHz
3. you can add these 2 members to usdhc node in device tree for debug purpose:
......
no-1-8-v; /* optional: if 3.3V IO is used, add it ,please! ; if 1.8V IO is used, comment it, please! */
max-frequency=<500000>; /* you can modify the value duiring debugging it. for example , 100M, 120M, 132M etc*/
......
Have a nice day!
B.R,
weidong