mipi csi2 dphy registers

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mipi csi2 dphy registers

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kurkinalexandr
Contributor III

Could you explain me some points related to MIPI_CSI_PHY_STATE in imx6.

First of all 9-th bit. Active low. Is that mean that clk lane in ULPS if the bit equal zero value?

8-th bit. Clock lane actively receiving a DDR cloclk. Is that bit mean(1-value) that imx6 DPHY module clock is correctly configured. In my case it is always zero value.

Thanks.

1 Solution
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igorpadykov
NXP TechSupport
NXP TechSupport

>Does it mean that imx6 mipi clock lane is in ULPS state if this bit equal zero?

yes

>Does it mean that it successfully receive clock from clk lane or from imx6 clock subsystem.

from clk lane

also from Debug steps for customer MIPI sensor.docx p.1

https://community.freescale.com/docs/DOC-94312

Tips:

In ov5640_mipi case (2 data lanes are used), the correct MIPI_CSI_PHY_STATE is

0x330 (and the bit 11 is jumping between 0 and 1, the value is jump between 0x330 and 0xb30).

View solution in original post

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Fan

MIPI_CSI_PHY_STATE bit 9 : Active Low. This signal indicates that the Clock Lane

module has entered the Ultra Low Power state.

Suggest to look at MIPI_D-PHY_Specification for understanding clock behaviour

in ULPS state.

8-th bit. Clock lane actively receiving a DDR cloclk. Right, this means

that imx6 DPHY module clock is correctly configured.

For clock configuration one can check document

Debug steps for customer MIPI sensor.docx

https://community.freescale.com/docs/DOC-94312

Best regards

igor

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kurkinalexandr
Contributor III

igorpadykov wrote:

Suggest to look at MIPI_D-PHY_Specification for understanding clock behaviour

in ULPS state.

I know what mean ULPS mode towards MIPI dphy specification. I am interested in what this bit mean for imx6. Does it mean that imx6 mipi clock lane is in ULPS state if this bit equal zero?

igorpadykov wrote:

8-th bit. Clock lane actively receiving a DDR cloclk. Right, this means

that imx6 DPHY module clock is correctly configured.

For clock configuration one can check document

Debug steps for customer MIPI sensor.docx

https://community.freescale.com/docs/DOC-94312

I investigated this document.  And configured CLK as it recommend. I also checked ¨mipi_pllref_clk¨ and ¨emi_clk¨  configuration. But I don`t understand still what mean 8-th bit.

What mean ¨actively receiving a DDR clock¨.  Does it mean that it successfully receive clock from clk lane or from imx6 clock subsystem. Continuing the previous question, must 8-th bit be set in case of switched off ADV7280-m dphy and switched on imx6 dphy?

What correct value should be set in MIPI_CSI_PHY_STATE register before switching on ADV7280-m dphy?

Thanks.

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205 Views
igorpadykov
NXP TechSupport
NXP TechSupport

>Does it mean that imx6 mipi clock lane is in ULPS state if this bit equal zero?

yes

>Does it mean that it successfully receive clock from clk lane or from imx6 clock subsystem.

from clk lane

also from Debug steps for customer MIPI sensor.docx p.1

https://community.freescale.com/docs/DOC-94312

Tips:

In ov5640_mipi case (2 data lanes are used), the correct MIPI_CSI_PHY_STATE is

0x330 (and the bit 11 is jumping between 0 and 1, the value is jump between 0x330 and 0xb30).

View solution in original post