line impedance for LPDDR4 on IMX8MP

[JeromeL]

Hello,

I have to route a LPDDR4 on an IMX8MPlus and I find contradictory information about line impedance.

In the hardware developer's guide, there is:

    - All single-ended signals, unless specified: 50 Ω Single-ended.

    - DDR DQS/CLK, PCIe TX/RX data pairs and reference clock: 85 Ω Differential.

And in the memory application note (from ISSI):

   - Clock: 70 Ω Differential.

   - ADD/CMD/CTRL: 40 Ω

   - DQ: 50 Ω

   - DQS: 83 Ω Differential

Do you have any recommandations ?

Regards,

Jérôme

[riteshmpatel]

Hi @JeromeL,

Hope you are doing well.
Please accept my apologies for the delay in response.

I have checked the EVK board design Layout and it follows the HDG document and has no issues in operation. Kindly follow the line impedance recommended in Hardware Design Guidelines. 

Thanks & Regards,
Ritesh M Patel