issue in reading input signals

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issue in reading input signals

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sapirbuz
Contributor IV

Hello,

We are using the MIMXRT1051CVL5B in our design.

We are encountering an issue with the p4, N4 and D6 pins.

We have configured those signals as input, and the MCU read always the same value, regardless of the real HW input.

P4- always read '1'

N4- always read '0'

D6- always read '1'

Could you please assist us in understanding why this issue is occurring?

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @sapirbuz,

Could you please provide more details about how you are configuring the pins, and how the hardware connection to these are being done? There is currently not enough information to clearly see if this is a hw or sw related issue.

BR,
Edwin.

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980件の閲覧回数
sapirbuz
Contributor IV

The pins are connected to TP, and we use an external power regulator to externally inject the required voltage through the TP (0V or 1.8V).

NVCC_SD=1.8V

It works the same way on our board and on the NXP EVKB (attached the schematics).

The configuration: Input, no pull up/down, no keeper

sapirbuz_0-1692195729755.png

 

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rudi_cyber
Contributor III

how about the iomux? could you please confirm the routing is correct.

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @rudi_cyber,

Of course. Share your IOMUX configurations and I can take a look into them.

BR,
Edwin.

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rudi_cyber
Contributor III

I just suggest to double confirm the iomux. Because the sdk default is following.

1.png

 

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @rudi_cyber,

Thanks for sharing the default IOMUX. I presume this is not the muxing you use for your application, however, since you are setting them up as inputs. At what point of your application are you setting these as inputs and how are you doing so?

BR,
Edwin.

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @sapirbuz,

Did you previously supply these pins in a manner that could cause damage to the pads? From your hw and sw description, there isn't anything in particular that stands out as the issue.

BR,
Edwin.

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