We are using two DDR3L in our design and want to interface with i.MX6Q using T- Topology. Can you please suggest me termination guidelines for Clock Signals?
About the DDRL design you can see the details https://community.nxp.com/message/1123328?commentID=1123328#comment-1123328
The termination is needed. About the termination recommend you to refer to our reference board design and follow it.