imxRT117x + IS25LP256E DTR mode

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imxRT117x + IS25LP256E DTR mode

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Jaivarthan
Contributor II

I am working on a custom board which uses RT117x MCU and the QSPI flash used is IS25LP256E.

I am trying to configure it to DTR operation (FRQDTR mode - EDh\EEh). As per the data sheet, I have set the dummy cycles as 6 in the QSPI read register and in the LUT command as well to execute at 69Mhz.

 

From this post i-MX-RT106x-IS25WP064D-QSPI-DDR-mode by  @jay_heng, I understand FlexSPI can operate at a maximum of 66Mhz even though the flash chip supports 80Mhz since flash chip has no dedicated DQS pin.

 

Below is the configuration I made for FRQDTR operation. But I could not have the application executing.

.controllerMiscOption = kFlexSpiMiscOffset_DdrModeEnable | kFlexSpiMiscOffset_SafeConfigFreqEnable,

.deviceType = kFlexSpiDeviceType_SerialNOR,

.sflashPadType = kSerialFlash_4Pads,

.serialClkFreq = kFlexSpiSerialClk_60MHz,

.lookupTable[0] = FLEXSPI_LUT_SEQ( CMD_SDR, FLEXSPI_1PAD, 0xEE, RADDR_DDR, FLEXSPI_4PAD, 0x20),
.lookupTable[1] = FLEXSPI_LUT_SEQ( MODE8_DDR, FLEXSPI_4PAD, 0x00, DUMMY_DDR, FLEXSPI_4PAD, 0x4),
.lookupTable[2] = FLEXSPI_LUT_SEQ( READ_DDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),

I wonder what is wrong in the configuration. 

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Jaivarthan
Contributor II

I am now able to execute my application in DDR mode at 75Mhz.

The issue was in the parameter .controllerMiscOption = kFlexSpiMiscOffset_DdrModeEnable | kFlexSpiMiscOffset_SafeConfigFreqEnable

where the value were enums and were not setting the correct bit values.

I have changed it as below: 

.controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) |(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable)

Also, the dummy cycle used in FDCB lookup table is twice the dummy cycle mentioned in the flash chip data sheet for DDR mode.

@Alexis_A Thanks for your support!

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Jaivarthan
Contributor II

I am now able to execute my application in DDR mode at 75Mhz.

The issue was in the parameter .controllerMiscOption = kFlexSpiMiscOffset_DdrModeEnable | kFlexSpiMiscOffset_SafeConfigFreqEnable

where the value were enums and were not setting the correct bit values.

I have changed it as below: 

.controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) |(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable)

Also, the dummy cycle used in FDCB lookup table is twice the dummy cycle mentioned in the flash chip data sheet for DDR mode.

@Alexis_A Thanks for your support!

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Alexis_A
NXP TechSupport
NXP TechSupport

Hello @Jaivarthan,

Looking at the configurations in the post the following one is also need it:

.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,

Also, in the same post explains the configurations need it for IS25LP but I think the configurations used are for the IS25WP. In one of the post mentioned explains the differences between these two memories.

Best Regards,

Alexis Andalon

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Jaivarthan
Contributor II

Hi @Alexis_A 

 

I have used the setting .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad and also set the dummy cycles in FDCB command to 12 (2*Dummy cycles for DTR mode). 

In the QSPI register, I tried setting dummy cycle with values 0 & 6. By default it supports 69Mhz in FRQDTR mode as per the data sheet. 

But still the application does not execute. 

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