imx93 lvds panel failed to create device link

[bora]

Hi everyone,

I'm working on enabling an LVDS panel on the i.MX93 custom board using Yocto and a custom device tree setup. I'm facing several issues during boot related to the display subsystem and LVDS panel connection. The config file I attached.

Any help or insights would be appreciated!

Thanks in advance!

here is the part of the lvds-panel dts configuration:

/ {

lvds_backlight: lvds_backlight {

compatible = "pwm-backlight";

pwms = <&tpm5 2 100000 0>;

//enable-gpios = <&adp5585gpio 8 GPIO_ACTIVE_HIGH>;

//power-supply = <&reg_vdd_12v>;

status = "okay";

brightness-levels = < 0  1  2  3  4  5  6  7  8  9

     10 11 12 13 14 15 16 17 18 19

     20 21 22 23 24 25 26 27 28 29

     30 31 32 33 34 35 36 37 38 39

     40 41 42 43 44 45 46 47 48 49

     50 51 52 53 54 55 56 57 58 59

     60 61 62 63 64 65 66 67 68 69

     70 71 72 73 74 75 76 77 78 79

     80 81 82 83 84 85 86 87 88 89

     90 91 92 93 94 95 96 97 98 99

    100>;

default-brightness-level = <80>;

};

lvds_panel {

        compatible = "panel-lvds";

        backlight = <&lvds_backlight>;

    data-mapping = "vesa-24";

        width-mm = <70>;

        height-mm = <52>;

        status = "okay";

port {

panel_lvds_in: endpoint {

remote-endpoint = <&lvds_out>;

};

};

        timing {

        clock-frequency = <6500000>;

                    hactive = <320>;

                    vactive = <240>;

                    hsync-len = <1>;

                    hfront-porch = <17>;

                    hback-porch  = <70>;

                    vsync-len    = <1>;

                    vfront-porch = <9>;

                    vback-porch  = <13>;

                    hsync-active = <0>;

                    vsync-active = <0>;

        };

};

};

&dphy {

status = "disabled";

};

&dsi {

status = "disabled";

};

&lcdif {

    status = "okay";

assigned-clock-rates = <445333333>, <6500000>, <400000000>, <133333333>;

};

&ldb {

status = "okay";

lvds-channel@0 {

status = "okay";

port@1 {

reg = <1>;

lvds_out: endpoint {

remote-endpoint = <&panel_lvds_in>;

};

};

};

};

&ldb_phy {

status = "okay";

};

These are the relevant boot log messages:

[ 0.348510] platform lvds_panel: Fixed dependency cycle(s) with /ldb-display-controller/lvds-channel@0
[ 0.877239] imx93-ldb ldb-display-controller: Failed to create device link (0x180) with 4ae30000.lcd-controller
[ 1.611948] imx93-ldb ldb-display-controller: Failed to create device link (0x180) with ldb-phy
[ 1.623932] panel-lvds lvds_panel: /lvds_panel: problems parsing panel-timing (-2)
[ 1.631550] panel-lvds: probe of lvds_panel failed with error -2

I also see repeated binding of imx-lcdifv3-crtc.0:

[ 0.868877] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
...
[ 19.317586] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 19.341381] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops)
[ 19.427728] platform imx-lcdifv3-crtc.0: deferred probe pending

[Zhiming_Liu]

Hi @bora 

Please use belwo setting whcih i have verified the generation of pixel clock

&lcdif {
	assigned-clock-rates = <45500000>, <6500000>, <400000000>, <133333333>;
};

New PLL:

PLL_FRACN_GP(45500000U, 15, 1, 6, 1, 8),

Best Regards,
Zhiming

[bora]

I tried and still doesnt work, but I tried on imx93 EVK on that it worked actually.I saw screen on the display.

[bora]

Hi,

I set it 6.5 MHz again and still doesnt work I see /dev/fb0. I attach also config file, if it helps.

[Zhiming_Liu]

Hi @bora 

Can you see any active signal on pixel clock interface and data line? Can you measure the real pixel clock on board?
Is there any other parameter need to be added into panel-timing referring the panel spec?

Best Regards,
Zhiming

[bora]

Hi ,
When I measure LVDS pins, the voltages are 0 V. Panel timing parameter added based on display timing table.

[Zhiming_Liu]

Hi @bora 

The timing in dts can't be parsed. Please refer panel-lvds in other dts, like below dts node.

panel {
		compatible = "panel-lvds";
		width-mm = <170>;
		height-mm = <28>;
		data-mapping = "jeida-18";

		panel-timing {
			clock-frequency = <49500000>;
			hactive = <800>;
			hback-porch = <48>;
			hfront-porch = <312>;
			hsync-len = <40>;
			vactive = <600>;
			vback-porch = <19>;
			vfront-porch = <61>;
			vsync-len = <20>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <1>;
		};

		port {
			panel_out_bridge: endpoint {
				remote-endpoint = <&bridge_out_panel>;
			};
		};
	};

Best Regards,
Zhiming

[bora]

Thank you for that but I still have these failures:

0.876581] imx93-ldb ldb-display-controller: Failed to create device link (0x180) with 4ae30000.lcd-controller
[ 1.606293] imx93-ldb ldb-display-controller: Failed to create device link (0x180) with ldb-phy
[ 1.618237] imx93-ldb ldb-display-controller: Failed to create device link (0x180) with panel

[Zhiming_Liu]

Hi,

These are noisy log, please ignore them.

To support a new LVDS panel, you need to modify the lcdif node.

&lcdif {
	assigned-clock-rates = <Pixel clock * 7>, <Pixel clock>, <400000000>, <133333333>;
};

Then modify the fracn_tbl in drivers/clk/imx/clk-fracn-gppll.c

PLL_FRACN_GP(455000000U, 151, 2, 3, 1, 8),

Best Regards,
Zhiming

[bora]

I modified lcdif
&lcdif {
status = "okay";
assigned-clock-rates = <42000000>, <6000000>, <400000000>, <133333333>;
};

and added
PLL_FRACN_GP(455000000U, 151, 2, 3, 1, 8), in the driver but with fb-test I dont see anything on the panel.

[Zhiming_Liu]

Hi @bora 

PLL_FRACN_GP(455000000U, 151, 2, 3, 1, is for Pixel clock=65MHz referring your original panel timing. Can you check and update your timing here?

Best Regards,
Zhiming

[bora]

I set it for 6.5MHz pixel clock and still didnt work. PLL_FRACN_GP(45500000U, 151, 2, 3, 1, 8). I can only set backlight

[Zhiming_Liu]

Hi,

Why is the pixel clock here not 6.5 Mhz? If you define 6.5 MHz in the panel-simple/panel-timing node, then the lcdif device tree needs to be synchronized here as well.

assigned-clock-rates = <42000000>, <6000000>, <400000000>, <133333333>;

Best Regards,
Zhiming

[bora]

Hi,

I set it again 6.5Mhz and still doesnt work. I see /dev/fb0 and I attach config file, if it helps