imx8qxp custom board dram configuration

[valentinraevsky]

Dear Support,

I'd appreciate it if you could help in configuring an MT53E2G32D4 using the MX8QXP_C0_B0_LPDDR4_RPA_1.2GHz_v16.xlsx referred: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8QXP-DXP-DX-DDR-Register-Programming...

The dram die addressing is: BA[2:0]; R[16:0]; C[9:0]. The xml file allows 14,15,16 row addresses only. What change has to be done in the document in order to configure the dram with R[16:0].

Regards,

Valentin.

[valentinraevsky]

Thanks for your fast reply.

1) Is this a limitation of the current soc i.MX8QXP implementation?
2) What is the reason of this limitation?

Regards,
Valentin.

[igorpadykov]

Hi Valentin

it is hardware limitation of i.MX8QXP DDRC (Synopsys IP) module.

Best regards
igor

[igorpadykov]

Hi Valentin

unfortunately 8GB LPDDR4 (as MT53E2G32D4) are not supported by i.MX8QXP, sorry.

Best regards
igor