on a custom board based on NXP i.MX8Q we are trying to use internal PCIE clock generation, but it seems not to work.
During kernel startup (using the scope) we can see the PCIE_SATA_REFCLK100M_P/ PCIE_SATA_REFCLK100M_N moving to an high level when bus scan starts, and going to low level et the end (few msec later), but no clock waveform is generated ...
If we use an external pci clock generator coming from the chip 9FGV0241AKLFT, everything works well, PCIE bus is correctly activated and PCIE devices are correctly detected.
So the problem is just in the internal pcie clock generation. Is there any extra configuration I need to use to activate it?
Here is the section I'm currently using in dts from kernel 4.14.98.
// ext_osc = <1>;
ext_osc = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
// clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
status = "okay";
one can try to update SCFW SCFW Porting Kit as following:
diff --git a/firmware/platform/board/mx8qm_mek/board.c b/firmware/platform/board/mx8qm_mek/board.c
index dc510f1..86dda91 100755
@@ -417,7 +417,7 @@ board_parm_rtn_t board_parameter(board_parm_t parm)
/* Used whenever HSIO SS powered up. Valid return values are
BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */
case BOARD_PARM_PCIE_PLL :
- rtn = BOARD_PARM_RTN_EXTERNAL;
+ rtn = BOARD_PARM_RTN_INTERNAL;
rtn = BOARD_KS1_RESUME_USEC;