imx8mqevk svga compatible

[Endo1]

I'm currently trying to connect to the display with SVGA using the imx8mqevk board, but it says "out of range" and I can't see it on the display.

What do I need to do to get it to display in SVGA?
The contents I have carried out are as follows.
Thanking you in advance.

Implementation content:

# Your i.MX Yocto Project Community BSP

Branch: imx-linux-gatesgarth
Manifest: imx-5.10.9-1.0.0.xml

# Your Linux kernel

Repository: https://source.codeaurora.org/external/imx/linux-imx.git
Tag: lf-5.10.y-1.0.0
Commit: 32513c25d8c7867f07b44900368346795357b48e

----
# Patch reference source

* Since it is for the Tradex version kernel, it could not be applied to the Community BSP version kernel as it is.

https://community.nxp.com/t5/i-MX-Processors/imx8mq-hdmi-custom-resolution-800x600-output-no-signal/...

----
#Implementation by us

* The second line of cdns-mhdp-hdmi-phy.c is https://community.nxp.com/t5/i-MX-Processors/HDMI-DRM-custom-resolution-and-clock-frequency/mp/ Calculated using the Excel file mentioned in 1029697 / highlight / true # M152124.

`` ```
diff --git a / drivers / gpu / drm / bridge / cadence / cdns-hdmi-core.c b / drivers / gpu / drm / bridge / cadence / cdns-hdmi-core.c
index 28193178140f..15c1522025c7 100644
--- a / drivers / gpu / drm / bridge / cadence / cdns-hdmi-core.c
+++ b / drivers / gpu / drm / bridge / cadence / cdns-hdmi-core.c
@@ -574,13 +574,6 @@ cdns_hdmi_bridge_mode_valid (struct drm_bridge * bridge,
if (mode-> hdisplay> 5120 || mode-> vdisplay> 2160)
return MODE_BAD_HVALUE;

-/ * imx8mq-hdmi does not support non CEA modes * /
--if (! strncmp ("imx8mq-hdmi", mhdp-> plat_data-> plat_name, 11)) {
--vic = drm_match_cea_mode (mode);
--if (vic == 0)
--return MODE_BAD;
-}
――――
mhdp-> valid_mode = mode;
ret = cdns_mhdp_plat_call (mhdp, phy_video_valid);
if (ret == false)

diff --git a / drivers / gpu / drm / drm_edid.c b / drivers / gpu / drm / drm_edid.c
index b7ddf504e024..21795f8b4d7b 100644
--- a / drivers / gpu / drm / drm_edid.c
+++ b / drivers / gpu / drm / drm_edid.c
@@ -1519,6 +1519,11 @@ static const struct drm_display_mode edid_cea_modes_193 [] = {
4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,},
+ / * 220 --800x600 @ 60Hz * /
+ {DRM_MODE ("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
+ 850, 950, 0, 600, 603, 605, 635, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,},
};;

/ *
@@ -3323,7 +3328,7 @@ static u8 * drm_find_cea_extension (const struct edid * edid)
static __always_inline const struct drm_display_mode * cea_mode_for_vic (u8 vic)
{
BUILD_BUG_ON (1 + ARRAY_SIZE (edid_cea_modes_1) --1! = 127);
--BUILD_BUG_ON (193 + ARRAY_SIZE (edid_cea_modes_193) --1! = 219);
+ BUILD_BUG_ON (193 + ARRAY_SIZE (edid_cea_modes_193) --1! = 220);

if (vic> = 1 && vic <1 + ARRAY_SIZE (edid_cea_modes_1))
return & edid_cea_modes_1 [vic -1];

diff --git a / drivers / gpu / drm / imx / mhdp / cdns-mhdp-hdmi-phy.c b / drivers / gpu / drm / imx / mhdp / cdns-mhdp-hdmi-phy.c
index f96b200885df..6936a8419afa 100644
--- a / drivers / gpu / drm / imx / mhdp / cdns-mhdp-hdmi-phy.c
+++ b / drivers / gpu / drm / imx / mhdp / cdns-mhdp-hdmi-phy.c
@@ -58,6 +58,8 @@ static const struct hdmi_ctrl imx8mq_ctrl_table [] = {
{27000, 27000, 1250, 337500, 337500, 0x03, 0x1, 0x1, 300, 0x0EC, 0x03C, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2, 2, 4, 0x3, 33750, 33750},
{27000, 27000, 1500, 405000, 405000, 0x03, 0x1, 0x1, 360, 0x11C, 0x048, 120, 0x03A, 0x03A, 3240000, 3240000, 0, 2, 2, 2, 4, 0x3, 40500, 40500},
{27000, 27000, 2000, 540000, 540000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x2, 54000, 54000},
+ {40000, 40000, 1000, 400275, 400275, 0x05, 0x1, 0x1, 593, 0x126, 0x127, 80, 0x026, 0x026, 3202200, 3202200, 1, 1, 1, 1, 1, 0x3, 40027, 40027} ,,
+ {40000, 40000, 1000, 400275, 400275, 0x05, 0x1, 0x1, 593, 0x1D7, 0x076, 80, 0x026, 0x026, 3202200, 3202200, 1, 2, 2, 2, 4, 0x3, 40027, 40027} ,,
{54000, 54000, 1000, 540000, 540000, 0x03, 0x1, 0x1, 480, 0x17C, 0x060, 80, 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3, 54000, 54000},
{54000, 54000, 1250, 675000, 675000, 0x04, 0x1, 0x1, 400, 0x13C, 0x050, 50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2, 67500, 67500},
{54000, 54000, 1500, 810000, 810000, 0x04, 0x1, 0x1, 480, 0x17C, 0x060, 60, 0x01C, 0x01C, 3240000, 3240000, 0, 2, 2, 2, 2, 0x2, 81000, 81000},
@@ -149,6 +151,7 @@ static const struct hdmi_pll_tuning imx8mq_pll_table [] = {
{10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4C, 219, 7, 272},
{11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258},
{12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244, 8, 292},
+ {13, 3202200, 3202200, 0x6, 0x3, 0x1, 0x00, 0x07, 593, 0x4C, 203, 7, 256}, / * nominal VCO freq: 3202200 * /
};;

/ * HDMI TX PLL tuning settings, pixel clock is input * /
`` ```

[joanxie]

do you mind sharing the logfile and your xls file with pixel clock calculation with me? let me check if your pixel clock setting is correct or not

[Endo1]

Share log and xls files.

[joanxie]

refer to your VOC, try to use this:

{ 14, 3202.1, 3202.3, 0x6, 0x3, 0x1, 0x00, 0x07, 593, 0x4C, 203, 7, 256 }, // nominal VCO freq: 3202.2

[Endo1]

I tried it but the problem didn't go away.

I also tried fixing vco_freq_min / vco_freq_max in imx8mq_ctrl_table, but that didn't fix the problem either.

Is there anything else I can try?

[joanxie]

refer to your calculate xls file, the pixel clock is 40028, how about change the 40000 to 40028? and try another 40014 and voc as below
165     { 19, 4001.3, 4001.5, 0x5, 0x3, 0x0, 0x07, 0x0F,  741, 0x42, 184, 6, 226 }, // nominal VCO freq: 4001.4

[Endo1]

I did what I was told, but the SVGA mode became unavailable and the problem was not resolved.
Maybe my implementation is bad.
I will attach a log, so please let me know if you notice anything.
Best Regards

[joanxie]

did you check pixel clk，phy clk from clk_summary? if no, pls dump them and check it

[Endo1]

Dumped clk_summary. The Reference Clock is 27MHz and the Pixel Clock is 40.00MHz, which looks fine.

> phy_27m 2 2 0 27000000 0 0 50000
> video2_pll1_ref_sel 2 2 0 27000000 0 0 50000
> video2_pll_out 1 1 0 40000000 0 0 50000

[joanxie]

could you confirm that your display can boot up successfully from other platform? I confirmed from vendor that they couldn't guarantee the display which isn't in the table can be boot up successfully , they only support the display can be found in the clock table

[Endo1]

If another platform is connected to the display, it will be displayed.
I understand that we do not guarantee displays that are not on the table.
thank you.

[Endo1]

thank you.
I will try.