I have noticed when using the Linux /sys/class/gpio interface one of my input gpios toggles from 0 to 1 occasionally. The input is held low constantly, but approximately every 5 minutes the input will toggle to 1 then immediately back. I am doing a read (cat /sys/class/gpio77/value) every 500 msec.
Digging around the documentation, I noticed in the i.MX 8M Plus Applications Processor Reference Manual, Rev2, 02/2024, section 8.3.5.1.2.2 there's a statement: "If a given GPIO direction bit is cleared, then a read of DR
register reflects the value of the corresponding signal. Two wait states are required in
read access for synchronization."
What wait states is this referring to?
Could this be the cause of the toggling I'm seeing?
Thanks,
Dean
