imx8mp: clock tree issue / main_axi

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imx8mp: clock tree issue / main_axi

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arno_0
Contributor III

Have two board (NXP-EVK and my development board) that behaves different in terms of clock. I use same latest NXP-kernel 5.15.71 and almost identical devicetree. There is nothing special related to clock in what is different in devicetree. In fact, the only difference is to use another phy at the eqos network interface.

Looking at /sys/kernel/debug/clk/clk_summary I see that parent clock of main_axi differs:

my board: osc_24m and clocks at only 12MHz.

evk board: sys_pll_800 and clocks at 400MHz.

The other major difference is ahb_clock. It has same parent but on my board just 22MHz, while evk board is on 66MHz. That has of course influence to all it's childs.

There are more differences ....

I am wondering what is the reason, although the kernel is exactly the same and devicetrees are sooo similar. Especially the clock controller is defined in same include: imx8mp.dtsi

(other differences are enet_phy_ref, enet_timer, enet_ref (all 25MHz) on my side hsio_axi.

Frankly speaking I don't understand what I can do and even with devicetree documentation I don't understand:

There are 6 clocks and a 10 assigned clocks, 7 assigned clocks parents and 10 clock rates (2 are zero !?!). How do they interact? Who controls that?

 

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mp-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
						  <&clk IMX8MP_CLK_A53_CORE>,
						  <&clk IMX8MP_CLK_NOC>,
						  <&clk IMX8MP_CLK_NOC_IO>,
						  <&clk IMX8MP_CLK_GIC>,
						  <&clk IMX8MP_CLK_AUDIO_AHB>,
						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
						  <&clk IMX8MP_AUDIO_PLL1>,
						  <&clk IMX8MP_AUDIO_PLL2>,
						  <&clk IMX8MP_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_ARM_PLL_OUT>,
							 <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL2_500M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <0>, <0>,
						       <1000000000>,
						       <800000000>,
						       <500000000>,
						       <400000000>,
						       <800000000>,
						       <393216000>,
						       <361267200>,
						       <1039500000>;
			};

 

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