No，it can not pass the DDR stress test ,and the uart shows:
Download is complete
Waiting for the target board boot...
===================hardware_init=====================
********Found PMIC PCA9450**********
hardware_init exit
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MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
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Waiting for board configuration from PC-end...
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
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ARM clock(CA53) rate: 1800MHz
DDR Clock: 1600MHz
============================================
DDR configuration
DDR type is DDR4
Data width: 32, bank num: 16
For DDR4, bank num is the total of 4 bank groups and 4 banks per group
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 8192MB
Density per controller is: 8192MB
Total density detected on the board is: 8192MB
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MX8M-plus: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @668Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1600Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS
============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1600MHz......Address of failure: 0x0000000040080040
Data read was: 0x0000000040008040
But pattern was: 0x0000000040000040
Failed
Please modify DDRC/DFI parameters!!!
