imx8mp can not boot up

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imx8mp can not boot up

1,217 Views
xjy198903
Contributor III

I have a self-made imx8mp board, use DDR4 memory, use yocto to compile the image and burn the SD card, the serial port output:

U-Boot SPL 2022.04-uboot_v2022.04-2.5.0+g5fb673f885 (Jun 25 2023 - 07:03:55 +0000)
DDRINFO: start DRAM init
DDRINFO: DRAM rate 3200MTS
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
SEC0: RNG instantiated
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
NOTICE: BL31: v2.6(release):lf-5.15.71-2.2.0-0-g3c1583ba0
NOTICE: BL31: Built : 11:00:38, Nov 21 2022

and stuck here

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8 Replies

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kenli
NXP Employee
NXP Employee

hello xjy198903

How is the current progress, is your board able to access ddr now?

Best regards
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1,207 Views
joanxie
NXP TechSupport
NXP TechSupport
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1,201 Views
xjy198903
Contributor III

No,it can not pass the DDR stress test ,and the uart shows:

Download is complete
Waiting for the target board boot...

===================hardware_init=====================


********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is DDR4
Data width: 32, bank num: 16
For DDR4, bank num is the total of 4 bank groups and 4 banks per group
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 8192MB
Density per controller is: 8192MB
Total density detected on the board is: 8192MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @668Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1600Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1600MHz......Address of failure: 0x0000000040080040
Data read was: 0x0000000040008040
But pattern was: 0x0000000040000040
Failed
Please modify DDRC/DFI parameters!!!

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1,175 Views
joanxie
NXP TechSupport
NXP TechSupport

I don't know how you set the PAR files, pls check if you set correct or not, more detailed information, pls refer to the link as below

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8MPlus-m865S-DDR-Register-Programmi...

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1,172 Views
xjy198903
Contributor III

I am using the 9th version of the DDR tool and configured it according to the chip manual in the attachment

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1,133 Views
joanxie
NXP TechSupport
NXP TechSupport
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1,131 Views
xjy198903
Contributor III

I've read that article, followed the tips above, and now my board keeps outputting in a loop:

xjy198903_0-1688017501303.png

It feels like the board is stuck in an endless loop

 

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1,113 Views
joanxie
NXP TechSupport
NXP TechSupport

at first, you need to use the DDR tool to regenerate new DDR script for your memory, then with the new timing file, you can apply it to your memory, btw, try to use

please set PHY_SDRAM_SIZE to 0xC0000000 and PHY_SDRAM_2_SIZE to 0x140000000

 

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