I attached a MIPI sensor to the imx8mp board. It uses 4 lanes and 8bit/pixel. Sensor has its own clock and it is master.
It turns out that mipi status register look fine up to a MIPI data speed of 700Mbps (each lane). If I go behind that 800 ... 1200Mbps I observe few or many (depending on speed) failure reports from MIPI_CSIS_INTSRC.
Is one of the clocks in imx8 to low? Which one is (or maybe more than one of the clocks are) responsible? I can exclude the quality of wiring/connection between sensor and board. I have two different setups, that behave in terms of this 700Mbps limit exactly the same.
For me MIPI seems the limit. What is it's clock, maybe it is to low in my application?
MIPI receives data and show CRC/ECC .. errror.
The ISI can handle up to 4K-res*24bpp*30fps (4k=8MPixel) = 5.76Gbps - less than 1.5Gbps with 4 lanes.
So why it shouldn't work with 1.2Gbps and 4 lanes? Maybe my clock-tree is not right? That is why I ask which clock and what frequency is used for this block.
Thanks four your answer. Where have you find that? I don't understand - isn't the CSI referrred to operate til 1.5Gbps?
The pixeldata rate in my uses case (for ISI that is next step after CSI, right) is only about 275 MPixel/s. Nevertheless I need a 1.2Gbps on 4 lanes for that (600MByte/s including overhead - that's why I use Byte not Pixel) - although here 1Pixel is 8bit.
This is because sensorchip processing depends on MIPI clock and there is no continuous pixel data (valid image data) transferred. So, there is some pause in between.
So, is it possible to feed the imx8mp with that? Sorry I didn't found that clear information about processor limit.