imx8mm spi clock format issue

[JunpapaCS]

Hello 

Precondition :

Old project: Imx7ulp, 

New project : imx8 (working on imx8mm EVK)

I'm porting the same device used on the previous project (imx7ulp), on the imx8mm EVK board through SPI I/F.
Even though spi module is working fine with testing through Loopback, the IC chip is not working properly.
I figured out the difference the Clock signal pattern of SPI between old one (imx7ulp) and new board (imx8).
that is the the image attached.
There's a gap (about 1.5 period) between every 8 bits TX  @ the previous board and chip. (this is working is fine)

@imx8mm EVK Board, there's no gap, the CLOCK signal changes with seamless. (I'm not sure this is a  reason, but the PCB test with the previous board is OK)

How can I make the clk signal pattern of SPI like the image attached ?

here's set infomation of SPI @ imx8mm EVK Board.

 /soc@0/bus@30000000/pinctrl@30330000/ecspi2cs
[ 1.365510] spi_imx 30830000.spi: registered master spi1
[ 1.365617] spi spi1.0: spi_imx_setup: mode 0, 8 bpw, 500000 hz
[ 1.365625] spi spi1.0: setup mode 0, 8 bits/w, 500000 Hz max --> 0
[ 1.370396] /soc@0/bus@30800000/spi@30830000/spidev@0: buggy DT: spidev listed directly in DT
[ 1.378982] WARNING: CPU: 3 PID: 1 at drivers/spi/spidev.c:731 spidev_probe+0x170/0x238

format worked

[JunpapaCS]

Hello Igor~

Thank you for the reply.
But I am looking for a solution directly related to the ECSPI2 port @EXP_CN on the imx8mm EVK board.
(Verified board, implemented on the LPSPI port of imx7ulp and the CLK DATA of the image is executed during once chip selection.)

[igorpadykov]

Hi JunpapaCS

one can try to adjust BURST_LENGTH in register ECSPIx_CONREG,

ECSPIx_PERIODREG described in sect.10.1 Enhanced Configurable SPI (ECSPI)

i.MX 8M Mini Applications Processor Reference Manual

Best regards
igor

[JunpapaCS]

Hello Again

When can I have a solution about 8 bit per work for spi module, @EXP CN, imx8mm EVK Board. 

Even though the set value of bpw is 8 (default) CLK signal generate continuous without a pause per every 8 bit.  (refer to the image  attached in post my first inquiry.) 

This is urgent

[JunpapaCS]

Hi

According to the set of bit per word (bpw), 0 or 8 ?, How does CLK's pattern work?
I'm suspecting that SPI CLK of imx8mm-evk SW(board) work as 0 of bpw even it looks 8 bpw in dmesg.
Anyone, please let me know the difference format when bpw is set 0 or 8 on imx board and software ?  

[JunpapaCS]

I doubt that bpw(bits per word) is work or not on imx8mm_evk.board (the default is 8 bpw) and imx-5-4_24-2-1.0.
I directly implemented the clk format pattern through controlling GPIOs, due to timeline issue for the project.
But I want to know why the bpw was not work as the set value.
mis-control or bugs