imx8mm MIPI DSI clock dividers

[steveschefter]

Hi.

There are two different registers which have settings for the P, M and S dividers associated with the MIPI DSI interface PLL:

GPR_MIPI_M_PLLPMS (part of DISPLAY_BLK_CTRL at base address 32E2_8000h) has PMS_P, PMS_M, PMS_S.

DSI_PLLCTRL (part of MIPI_DSI at base address 31E1_0000h) has PMS.

First question: how do these two registers relate to one another?

I would like to use spread spectrum with the display interface.  The Linux driver drivers/gpu/drm/bridge/sec-dsim.c uses the second of the two registers indicated above to set PMS.  However, the SSCG_EN bit to enable spread spectrum is part of GPR_MIPI_M_PLLCTL_LOW.

Second question: If setting the SSCG_EN bit, do the PLL divisors have to be set up using the DISPLAY_BLK_CTRL block, or can SSCG_EN be set in GPR_MIPI_M_PLLCTL_LOW while the above driver sets up the rest of the PLL?

Or more generally, how does one initialize the PLL when using spread spectrum?

Thanks,
    Steve

[steveschefter · Accepted solution]

For P, M, S, we stuck with DSI_PLLCTRL as is written by the Linux driver drivers/gpu/drm/bridge/sec-dsim.c.

For the spread spectrum part we found that using the GPR_MIPI_M_PLLCTL_LOW and _HIGH registers does not work.  No dither was observed.  However, one of the other guys figured out that using DSI_PLLCTRL1 and DSI_PLLCTRL2 (32E1_0098, 32E1_009C) does work.  The RM does not detail the bits in those registers, but using the arrangement described for GPR_MIPI_M_PLLCTL_LOW and GPR_MIPI_M_PLLCTL_HIGH worked.

[joanxie]

if you need set P, M,S, set the GPR register, I mean GPR_MIPI_M_PLLPMS