Hi.
Need help with configuration.
Downloading file 'bin\lpddr4_train1d_string_v201709.bin' ..Done
Downloading file 'bin\lpddr4_train2d_string_v201709.bin' ..Done
Downloading file 'bin\lpddr4_imem_1d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_dmem_1d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_imem_2d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_dmem_2d_v201709.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done
Download is complete
Waiting for the target board boot...
===================hardware_init=====================
********Found PMIC BD718XX**********
hardware_init exit
*************************************************************************
*************************************************************************
*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:30:14
*************************************************************************
Waiting for board configuration from PC-end...
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x93d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 1500MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================
MX8M-mini: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1500Mhz...
PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x1000 ****
PMU10: Setting boot clock divider to 28
PMU10: PHY TOTALS - NUM_DBYTES 2 NUM_NIBBLES 4 NUM_ANIBS 10
PMU10: CSA=0x01, CSB=0x00, TSTAGES=0x131F, HDTOUT=5, MMISC=0 DRAMFreq=3000MT DramType=LPDDR4
PMU10: Pstate0 MRS MR1_A0=0x00D4 MR2_A0=0x002D MR3_A0=0x0031 MR4_A0=0x0000
PMU5: CA bitmap dump for cs 0
PMU5: CAA0 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA1 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA2 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA3 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA4 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA5 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
It tries to refer to Bank A(connected to LPDDR4 bank B) but it is not present.
RPA config:
