imx8m USDHC and adma2

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imx8m USDHC and adma2

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NeilShipp-MSFT
Contributor II

In the imx8m reference manual, the section for the USDHC controller is a direct copy and paste of the IMX7D documentation and only covers 32 bit mode addressing.  Does the imx8m USDHC controller support 96 bit length ADMA2 descriptors and 64 bit addressing?  If not, that means all SDHC ADMA transfers to and from memory above 0xFFFF FFFF will need to be double buffered.

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NeilShipp-MSFT
Contributor II

As a followup question, are there any special way memory must be configured to allow USDHC ADMA2 to read and write to memory blocks?  I'm seeing a problem where the ADMA status register always returns error 9 if the descriptors are in DRAM (0xBFFE7000, 0x559b4000 are examples), but succeeds if I set it up to read from OCRAM_S 0x180000.  The RDC appears to be setup to allow all domains access to all memory.

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NeilShipp-MSFT
Contributor II

I found the issue with the ADMA status register error.  The DRAM memory being used for the ADMA descriptors wasn't being marked as non-cacheable.

I'm still interested in NXP's guidance on the use of DRAM above 0x1 0000 0000 since it's not accessible via DMA and many of the on-board peripherals.

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diegoadrian
NXP Employee
NXP Employee

Hello,

Let me see if internally they know the answer to your problem.

I will come as soon as I have an answer.

Best Regards,

Diego.

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diegoadrian
NXP Employee
NXP Employee

Hello,

I apologize for the delay.

From the RM memory map, the upper 1GB (0x1_0000_0000 - 0x1_3FFF_FFFF) is only accessible from Quad-A53. All the IP except the A53 can only support up to 32-bit address (0xFFFF_FFFF), so the on-board peripherals, including USDHC, won't have access to this region.

 

A53 should access the upper 1GB region without any DMA acceleration.

Hope this information can help you.

Best Regards,

Diego.

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