In the imx8m reference manual, the section for the USDHC controller is a direct copy and paste of the IMX7D documentation and only covers 32 bit mode addressing. Does the imx8m USDHC controller support 96 bit length ADMA2 descriptors and 64 bit addressing? If not, that means all SDHC ADMA transfers to and from memory above 0xFFFF FFFF will need to be double buffered.
As a followup question, are there any special way memory must be configured to allow USDHC ADMA2 to read and write to memory blocks? I'm seeing a problem where the ADMA status register always returns error 9 if the descriptors are in DRAM (0xBFFE7000, 0x559b4000 are examples), but succeeds if I set it up to read from OCRAM_S 0x180000. The RDC appears to be setup to allow all domains access to all memory.
I found the issue with the ADMA status register error. The DRAM memory being used for the ADMA descriptors wasn't being marked as non-cacheable.
I'm still interested in NXP's guidance on the use of DRAM above 0x1 0000 0000 since it's not accessible via DMA and many of the on-board peripherals.