Hello
I have a pin_mux.dts file generated by Pins tool which contains these two lines:
SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20000040
SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020
The two macros are defined in pads-imx8qxp.h like this:
#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
where 4 means ALT4, I think.
According to Page 1026 of i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual,
bits 29-27 of the pad/mux control register for QSPI0A_SS0_B mean:
mux_mode
000b - LSIO_QSPI0A_SS0_B
100b - LSIO_GPIO3_IO14
In that case, why is 0x00000020, rather than 0x20000020, generated by Pins tool for SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14.
Is it because the definition of SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 has already contained the number 4?
If that's the case, why is 0x20000040, rather than 0x00000040, is generated for SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16?
Another question is:
According to the Reference Manual, bits 31 and 30 of the mux/pad control register mean
bit 31
update lock for mux control
write 1 to allow programming to mux control [29:19]
bit 30
update lock for pad control
write 1 to allow programming to pad control [14-1:0]
What does 'write 1 to allow programming' mean here?
For example, in the case of above-mentioned 0x00000020, the bits 29:19 and 14-1:0 are actually useless/ignored, aren't they?
