When attempting to configure our product that can use an imx8m mini or imx8m nano we want to be able to use the BSDL files associated with each to test the part during manufacturing at in-circuit test.
The BSDL file works fine for the imx8m mini.
The Nano not being fully 1149.1 compliant is presenting an issue.
As mentioned in the i.MX8M Mini to i.MX8M Nano Design Compatibility Guide we are following this instruction.
We use 4.7k resistors in the ICT test fixture with relays so that the 4 signals mentioned will be pulled high to a logic "1" when the board is powered up. JTAG_Mod will be pulled to a logic "0" via a 4.7k termination resistor.
While the Nano bsdl appears to work, an unwelcome side effect is that the VDD_SNVS_0V8 is 0.945 volts instead of 0.8 volts.
Anyone have a reasoning for something like this?
We don't see this with the imx8m mini because we do not have to set up relays prior to power up as it uses the compliance pins in the BSDL file and works correctly.
The PMIC we use for both the imx8m mini and imx8m nano is the BD71847amwv
SOM i.MX8Mnano EVK LPDDR4
“Boundary scan testing of an LPDDR4 connected to the iMX8M Nano is failing. This appears to be because the LPDDR4 is being held in reset through pin R1 of the iMX8M Nano (DRAM_RESET_N), which is a linkage pin and therefore inaccessible from boundary scan. The iMX8M is actively driving the signal, so fitting a pull-up does not resolve the problem. Is there any way to use JTAG to change the state of this pin so that it remains high during boundary scan tests?”
Hello Yuri, sorry for the delay, I was on holiday.
I cannot understand well your answer. I suppose you mean that LPDDR4 has not a BSCAN test by itself, but my BSCAN test producer has developed some behavior libraries so that we can test the memories through the Micro interface bus. In this case, if the memory is held on reset state, it is not responding to stimuli.
I would need to "unlock" the RAM.
Yuri, here's the comment of our BSCAN test provider:
“You are correct that LPDDR4 does not include a TEN pin. However, XJTAG have successfully tested connectivity to LPDDR4 devices using boundary scan in other designs (e.g. imx8mmini). The thing preventing them from doing the same from the iMX8M Nano is the DRAM_RESET_N being driven low. Therefore, is there any way to use JTAG to change the state of this pin so that it remains high during boundary scan tests?”
We checked out the termination/relay setup against 2 versions that use the imx8 mini and the VDD_SNVS_0V8 remained in specification.
Only the Nano version when we use the termination/relay setup to enter boundary scan mode demonstrates the VDD_SNVS_0V8 being out of specification, but if we power up the board without the relay/termination setup the VDD_SNVS_0V8 on the Nano version IS in specification.