imx7d tce underrun problem

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imx7d tce underrun problem

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Contributor III

Dear nxp,

We use imx7d processor with eink 10.3 inch panel, and we are puzzled by the tce underrun problem.

We found that imx7d uboot has set the epdc qos priority like follows, but we do not know if it is right.

arch/arm/cpu/armv7/mx7/soc.c in u-boot:

static void set_epdc_qos(void)
{
#define REGS_QOS_BASE     QOSC_IPS_BASE_ADDR
#define REGS_QOS_EPDC     (QOSC_IPS_BASE_ADDR + 0x3400)
#define REGS_QOS_PXP0     (QOSC_IPS_BASE_ADDR + 0x2C00)
#define REGS_QOS_PXP1     (QOSC_IPS_BASE_ADDR + 0x3C00)

        writel(0, REGS_QOS_BASE);  /*  Disable clkgate & soft_reset */
        writel(0, REGS_QOS_BASE + 0x60);  /*  Enable all masters */
        writel(0, REGS_QOS_EPDC);   /*  Disable clkgate & soft_reset */
        writel(0, REGS_QOS_PXP0);   /*  Disable clkgate & soft_reset */
        writel(0, REGS_QOS_PXP1);   /*  Disable clkgate & soft_reset */

        writel(0x0f020722, REGS_QOS_EPDC + 0xd0);   /*  WR, init = 7 with red flag */
        writel(0x0f020722, REGS_QOS_EPDC + 0xe0);   /*  RD,  init = 7 with red flag */

        writel(1, REGS_QOS_PXP0);   /*  OT_CTRL_EN =1 */
        writel(1, REGS_QOS_PXP1);   /*  OT_CTRL_EN =1 */

        writel(0x0f020222, REGS_QOS_PXP0 + 0x50);   /*  WR,  init = 2 with red flag */
        writel(0x0f020222, REGS_QOS_PXP1 + 0x50);   /*  WR,  init = 2 with red flag */
        writel(0x0f020222, REGS_QOS_PXP0 + 0x60);   /*  rD,  init = 2 with red flag */
        writel(0x0f020222, REGS_QOS_PXP1 + 0x60);   /*  rD,  init = 2 with red flag */
        writel(0x0f020422, REGS_QOS_PXP0 + 0x70);   /*  tOTAL,  init = 4 with red flag */
        writel(0x0f020422, REGS_QOS_PXP1 + 0x70);   /*  TOTAL,  init = 4 with red flag */

        writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */
}

We also enable the priority elevation mechanism in linux kernel by set the EPDC register EPDC_FIFOCTRL bit31.

All above can not resolve the tce underrun problem, do you have some suggestions and experience

Thanks a lot!

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NXP TechSupport
NXP TechSupport

Hi Hou

nxp uboot has optimal epddc settings:

mx7dsabresd.c\mx7dsabresd\freescale\board - uboot-imx - i.MX U-Boot 

However for optimal performance of custom epd panel custom firmware may be needed,

as described in sect.6.4.5.8 Using a Custom Waveform File attached Linux Manual.

Best regards
igor
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Contributor III

Hi igorpadykov

 

Thanks for your response!

But we have alreay used our custom firmware:epdc_ES103TC1.fw

And we got the tce underrun problem in linux kernel when app have updates, it is ok in uboot!

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Contributor III

Hi igorpadykov

Thanks for your response!

But we have alreay used our custom firmware:epdc_ES103TC1.fw

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