imx7d WDOG Reset PMIC Inconsistencies

[davidwightman]

I am having some reset issues with the imx7d and PFuze PMIC (PF3000).  I have the external WDOG connected to the PMIC PWRON, and am trying to do controlled resets using reboot commands or from a wdog event.

Most of the time after doing a power cycle, if I try and do a reset with the "reboot" command in linux or "reset" command in uboot, the board freezes.  When I probe the PWRON/WDOG_B signal, it seems like this event happens okay.  Then the POR is asserted, but then is never released, which I assume is the reason things freeze.  Doing more toggles of the PMIC PWRON with a switch doesn't bring it out of this state, and only a power cycle can clear it or if I hard pull the POR signal to Vcc (Using an ext. 100k pull up isn't enough).  Occasionally, the board will proceed with the reset after many minutes of sitting in this state, but that is not reliable.

It seems like the PMIC is not releasing the POR for some reason.  The PWRON_CFG=0.

Other times, for no apparent reason, the reboots happen okay.  Once I can get a reboot to work once, then every subsequent time, wdogs and reboots seems to work as expected until I do a power cycle.  

Is there something that could prevent the PMIC from releasing the POR after a PWRON pulse (PWRON goes low then high within ~10m - 20Sec)? Unless the SoC itself is preventing the POR from going high.

[Yuri]

Hello,

  Is it possible to look at the connection scheme between WDOG and  PMIC PWRON?

Also look at erratum e10574 (Watchdog: A watchdog timeout or software trigger will not

reset the SOC).

https://www.nxp.com/docs/en/errata/IMX7D_2N09P.pdf 

Regards,

Yuri.

[davidwightman]

Hi Yuri,

The main difference between my setup and the Sabre is that I have the WDG_RST_B signal tied directly to the PMIC_PWRON, rather than passing through a TPS3808G30 (refdesignator U37 on the sabre schematics).  So possibly the hold down of the WDG_RST_B is not long enough if it is connected directly to the PMIC_PWRON, although I haven't seen any requirements around this.  I am going to order some of the TPS3808G0's and deadbug them into my board to see if that is the main problem.  But this just takes a little time to order in and test.

One other difference is that although I have the memory power rails gated like on the sabre, I do not use a separate supply for 3V3 peripherals, and do not gate those peripherals power based on the POR_B.  I do have two ENET PHYs that have their reset lines tied to the POR through schottky diodes.

[Yuri]

Hello,

  Also CR circuit (C382 R349), which forms signal is important.

Regards,

Yuri.