Hello!
Using imx7d.
Our CPU is connected to an external phy via RMII.
We have a RMII hold time violation because the RMII phy does not accommodate for the 2ns holdtime expected by the imx7d RMII RX[0..1] inputs. imx7d samples RX with the rising edge of REF_CLK input.
BUT the phy changes its TX[0..1] ouputs only a few 100ps after the rising edge of the REF_CLK.
So there is not much hold time left and some times an ethernet crc error happens.
Enabling hysteresis on imx7d RMII RX inputs, but keep it disabled on the REF_CLK input helps to improve the situation, because the RX signals get delayed by the activated hysteresis.
AN5078: 4.2 HYS: states:
The voltage levels are based on half of the power supply – see Table 4. The transition from logic 0 to logic 1 occurs only when the input signal is higher than half of the power supply voltage plus half of the
hysteresis and vice versa. There is no intermediate level like on the CMOS input.
Compared to the CMOS configuration option, the HYS one slightly increases the pin power consumption
"as well as the propagation delay by several nanoseconds."
I could not find any information about the AC parameters in the datasheet.
Is there some more information about the imx7d hysteresis function?
Is this propagation delay caused by the higher / lower transition points?
Or is there some additional internal chip delay? How much nanoseconds?
IMX7DRM only shows the bit to enable the io pad hysteresis mode.
IMX7DCEC only states the io dc characteristics hysteresis voltage: Vhys min. 150mV
See also: https://community.nxp.com/t5/i-MX-Processors/GPIO-DC-AC-timing-parameters-in-Schmitt-trigger-mode/m-...
Thanks in advance!
