Hi,
I'm trouble in interfacing between FEC and TJA1100 phy.
my test environment is:
- i.mx6ull
- linux 4.9.11
- MII mode ( 4bits data, 100M duplex, 25MHz txc/rxc as separate clock)
with current driver, receive part is working well from PC to RAD Moon(Signal converter) to target board.
when PC side sends ping command to target board, it responds to ping command properly by checking data with tcpdump tool. and target board side shows ping reply response correctly, but actual transmission failed to reply ping for PC side. that's why transmission data is not working well from FEC to Phy.
I've captured some waveforms by using CRO.
FEC test environment is:
- tx data: data 10 alternate , for example, 10100101( 0x5a)
- digital loopback(PCS block) in TJA1100
- txd pin, rxd pin captured by CRO
if data can be generated 1010 alternate at FEC side, drivers/net/ethernet/freescale/fec_main.c, I could see data at each TXD0,1,2,3.
as you see, tx data seems to be fed into phy without problem, but the resultant digital loopback data are shown some 1s string and other 0s except single normal output.
[FEC TX data from imx6ull ]
[RX data from phy after digital loopback]
and I've tried to narrow down this problem in terms of tx data and tx clock.
data is clocked on rising edge for 10M/100Mbps. strangely, data 10 alternate was generated on rising and falling edge synchronous. I've tried to look at reference manual and fec_main.c, failed to fix it except FEC_QUIRK_HAS_GBIT at fec_main.c. that's why 1GBS data is clocke on both(falling/rising)edge synchronously.
here's the problematic waveform by CRO
- yellow line: tx clock
- green line: tx data
[all 1's data captured at Phy side, though tx data 10 alternate transmitted at FEC side]
[all 0's data captured at Phy side, though tx data 10 alternate transmitted at FEC side]
do you have patch driver for fixing it up?
please, refer to current fec driver as attached( linux4.9.11 )
Thanks in advance.
Solved! Go to Solution.
Hi Igor,
due to your support, this issue has been resolved!.
my target board with i.mx6ull has used reference linux source code with KSZ8081( reference phy device).
this ethernet phy device works on RMII(50MHz), but I use TJA1100 as MII(25MHz).
linux/drivers/clk/imx/clk-imx6ul.c:
clk_set_rate(clks[IMX6UL_CLK_ENET_REF],50000000);
==>
clk_set_rate(clks[IMX6UL_CLK_ENET_REF],25000000);
now, after fix up, ping test is working well.
Thanks again,
DaeYun.
Hi Igor,
due to your support, this issue has been resolved!.
my target board with i.mx6ull has used reference linux source code with KSZ8081( reference phy device).
this ethernet phy device works on RMII(50MHz), but I use TJA1100 as MII(25MHz).
linux/drivers/clk/imx/clk-imx6ul.c:
clk_set_rate(clks[IMX6UL_CLK_ENET_REF],50000000);
==>
clk_set_rate(clks[IMX6UL_CLK_ENET_REF],25000000);
now, after fix up, ping test is working well.
Thanks again,
DaeYun.
i.MX6ULL EVK doesn't have any TJA1100 phy driver in terms of ethernet interface.
instead, I've summarized this FEC issue as follows.
1. FEC interface
- 4 bits TX Data: TXD[0...3] as FEC --> TJA1100
- TXC: tx clock(25MHZ) as FEC <-- TJA1100
this FEC data should be transmitted according to TXC(tx clock) generated by TJA1100.
i.mx6ull reference manual has also this description(IMX6ULLRM.pdf):
TX data are synchronous to TX Clock rising edge
additionally, TJA1100 has also the same behaviour:
TJA1100 expects that FEC data should be synchronous to TX Clock rising edge as well.
2. FEC/PHY Timing diagram
2.1 the expected and ideal behaviour btw FEC tx data and TJA1100 tx clock
if you would send 101010..... data, you must see tx clock and tx data,
that is, TXD data value can be changed to TX clock rising edge as follows:
2.2 the actual & problematic behaviour btw FEC tx data and TJA1100 tx clock.
actual tx data value was changed to TX clock rising/falling edge with 101010.... data sequence.
TJA1100 must see this TX data as all 1's all the time.
3. DTS data for IOMUX pins.
- 4 bits tx data
- tx clcok
- 4 bits rx data
- rx clcok
if you think that problem in FEC driver, this should not depend on TJA1100 phy
or any other external chip. Specific software changes for TJA1100 can be found in:
linux.git - Automotive Linux Tree
You can use NXP Professional Services for getting help with developing this custom driver:
NXP Professional Services|NXP
Best regards
igor
Hi Igorpadykov,
this problem depends on FEC driver rather than Phy driver.
Phy device generates 25MHz tx clock properly, and FEC data should sends tx data[0..3] on tx clock rising edge.
but actually imx6ull FEC device now outputs tx data on both falling/rising edge like 1000 Mbps link speed.
here's my ported driver for linux version 4.9.11
though FEC problem, now, I've tried to slow down the link speed from 100 Mbps to 10 Mbps in phy driver.
I expected that 100 Mbps mode has 25MHz tx clock and 10 Mbps mode has 2.5MHz tx clock.
but after changing to 2.5MHz tx clock, I've checked actual tx clock and tx clock showed 25MHz instead of 2.5MHz
can TJA1100 change the link speed from 25MHz to 2.5 MHz in terms of 10 Mbps speed?
here's phy driver mode:
- managed mode
- 10Mbps
- Basic control register: tried to set register with 00(10Mbps), 01(100Mbps)
/* Configures the autonegotiation capabilities */
static int nxp_config_aneg(struct phy_device *phydev)
{
if (verbosity > 0)
phydev_err(phydev, "configuring autoneg\n");
/* disable autoneg and manually configure speed, duplex, pause frames */
phydev->autoneg = 0;
phydev->speed = SPEED_100; // <- can be changed with SPEED_10
phydev->duplex = DUPLEX_FULL;
phydev->pause = 0;
phydev->asym_pause = 0;
return 0;
}
if you think that problem in FEC driver, could you try
to reproduce issue on i.MX6ULL EVK with NXP Demo images
https://www.nxp.com/webapp/Download?colCode=L4.9.11_1.0.0_iMX6UL7D&appType=license&location=null
Best regards
igor
Hi DaeYun
please look at driver sources for this chip and add necessary changes to
custom codes
linux.git - Automotive Linux Tree
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------