imx6ull SPI Performance issue

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imx6ull SPI Performance issue

171 Views
Contributor I

Hi,

We are using 4.1.15 linux kernel on imx6ull platform.

We are facing below issues in our platform,


1.when we are testing with SPI data transfer we observed there is a huge delay ( ~9.5us ) between chip select and MOSI line . Even after data transmission there is huge delay( ~35 us ) in making the chip select high. Please let us know how to reduce this delays in kernel. Please find the attached Logic analyzer image.
2.Also, we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ, throughput is very less in 18MHZ compared to 5MHZ.Please where to find patches to increase the throughput in linux kernel. 
3. Presently we are using PIO for data transfer. please let me know, were we will find the patches to enable/configure DMA & Burst transfer in SPI.

Thanks & Regards,
Sheik

 

 

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7 Replies

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NXP TechSupport
NXP TechSupport

Hi Sheik

 

- one can try patch for eCSPI native CS lines

https://patchwork.kernel.org/patch/10044381/

 

-  use dts "dmas" :

 

https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/spi/fsl-...

Best regards
igor

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144 Views
Contributor I

Hi,
1.As you suggested to apply the below patches is already taken care in our spi-imx.c driver, please refer the attached driver for your reference
2.Also we are using "dmas" in our dts file.

Below are the dts changes we have done in our side,

ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ECSPI1>,
<&clks IMX6UL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "okay";
};

3.I have attached our spi-imx.c driver file for your reference.

Please provide us any other suggestion so that we could able to improve SPI performance.

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NXP TechSupport
NXP TechSupport

unfortunately  it is not possible to further reduce these delays,

as it is defined in hardware (hardware limitation).

 

Best regards
igor

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116 Views
Contributor I

Thank you for valuable input. We understood the limitation in chip-select.

we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ, throughput is very less in 18MHZ compared to 5MHZ.Please let us know what could be the reason behind this and also patches to increase the throughput in linux kernel if available.

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NXP TechSupport
NXP TechSupport

>we need to know when we are setting the SPI clock frequency from 5MHZ to 18MHZ,

>throughput is very less in 18MHZ compared to 5MHZ.

 

mentioned delays are caused by internal processor delays, not related directly to SPI clock frequency.

 

Best regards
igor

 

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98 Views
Contributor I

Thanks for your quick response.

When we are setting frequency to 5MHZ and we are able to receive 300 data packets per second but with 18MHZ we are getting only 150 data packets. Could you please tell us the reason behind this drop.

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NXP TechSupport
NXP TechSupport

>Could you please tell us the reason behind this drop

 

please recheck ecspi settings in both cases. Test performance with the same

settings in both cases.

 

Best regards
igor

 

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