imx6ul sai timeslot issue

[chenandy]

Hello,

    Added an additional si32176 and 4G module on my board to sai3.

    asynchronous, TX Frame Sync Direction externally, RX Frame Sync Direction internally, TX and RX Bit Clock Direction externally.
    The first timeslot starts at the falling edge of fs, but I want to imx6ul the first timeslot starts at the rising edge of fs, what can  I do?

                                                                         this is imx6ul sai txdata timeslot

                                                                 I expect the result

Thanks in advance,

Andy

[igorpadykov]

Hi Andy

>I want to imx6ul the first timeslot starts at the rising edge of fs, what can  I do?

there is option of changing Frame Sync Polarity using FSP bit I2Sx_TCR4 register,

other sai timings can not be changed as they defined in hardware. More details

can be found in sect.42.3.4 Frame sync configuration i.MX 6UltraLite Applications Processor Reference Manual

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------