imx6sx move OCRAM from using PLL2 to PLL3

[AaronDev]

Hello,

We are using a custom board with the i.MX6SoloX, and have a need to change the frequency of PLL2. Due to the DDR also using PLL2, we needed to enable SPL code in U-Boot so we could change the PLL2 before the DDR was initialized. According to the Clock Root Generator diagram in the RM, OCRAM is by default suppose to be sourced from PLL3, but it looks like our processor is using PLL2. I'm guessing this default is setup in the ROM code? Is it possible to move the OCRAM source clock to PLL3 or Bypass PLL2 and use the (24Mhz base clock) "while" we're running from OCRAM? If so, would there be some sample code to do so?

Thanks!

[JorgeCas]

Hello,

There are some limitations to do modifications in PLLs:

In order to modify or stop the clock output of a specific PLL, all the clocks generated from the current PLL must be transitioned to the new PLL whose frequency is not being modified.

For clocks which can't be stopped (core and bus clocks), this should be done via the glitchless mux. Before changing the PLL setting, power it down. Power up the PLL after the change.

In order to ensure a robust operation of the processor, it is recommended to use the original BSP configuration. In our BSP a software reset is required after setting the new PLL rate, that’s why a PLL power down/up and this is configured here:

linux-imx/drivers/clk/imx/clk-imx6sx.c at 37d02f4dcbbe6677dc9f5fc17f386c05d6a7bd7a · nxp-imx/linux-i...

Best regards.