imx6sx DDR cacheability

[catalinzafiu]

Hello Everybody,

I have a bare-metal code running on M4 core.

The core executes, from DDR, much slower than expected, that means more than 10 times slower than executing from TCM.

I suspect the cache is not properly configured.

The cache controller is enabled using the LMEM_EnableSystemCache() and LMEM_EnableCodeCache() provided by NXP on FreeRTOS example.There is no effect for execution time after calling LMEM functions.

I did not find anything about cacheability.

Is there any way to define/check the DDR cacheability for M4? I mean to define DDR regions as cacheable/non-cacheable.

Thanks

[Yuri · Accepted solution]

Hello,

  The base address of LMEM is 0xE008_2000.

The RM in section 13.11 (LMEM Memory Map/Register Definition) contains

misprints.

Have a great day,
Yuri

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[catalinzafiu]

Thanks Yuri,

I have updated the base address. The cache is working now, the execution time is as expected.

After enabling the cache, the Segger J-Link debugger seems not able to stop in breakpoints. Do you have any hint for that?

Regards,

Catalin

[johnesmith]

Hi, as I understood the cacheability has effect on the whole DDR region, right? Is it possible to enable the cacheability for a specified DDR region?

[Yuri]

Hello,

  perhaps the problem concerns with the fact, that cache coherency

is not provided in i.MX6 SX. The debugger is working in physical addresses.

Regards,

Yuri.

[catalinzafiu]

Thanks Yuri