imx6q sabre AI board MIPI camera.

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imx6q sabre AI board MIPI camera.

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Contributor IV

Hi all,

I am trying to write a custom mipi camera module connect to imx6q sabre auto board.

The custom camera's details is as bellow:

4 data lanes,

YUV422 8 bit data format,

And it is no need to send any control command to camera module(it will work when power on)

And I referenc the ov5640_mipi camera driver, and delete the source code about I2C control.

Now, the problem is that when i excute the /unit_tests/mxc_v4l2_capture.out as follow:

./mxc_v4l2_capture.out -d /dev/video1

I got the errors message:

ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0

VIDIOC_DQBUF failed.

ERROR: v4l2 capture: VIDIOC_QBUF: buffer already queued

And I got the MIPI registers value:

0x021DC000:  3130302A 00000003 00000001 00000001

0x021DC010:  00000001 000002F0 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

I found that ov5640 camera on sabre sd board, the values are:

0x021DC000:  3130302A 00000001 00000001 00000001

0x021DC010:  00000001 00000330 00000000 00000000

0x021DC020:  00000000 00000000 00000000 00000000

0x021DC030:  00000000 00001414 00000000 00000000

The address 0x021DC014 register's bit 8 is different. (this bit Indicates that the clock lane is actively receiving a DDR clock)

I am not clearly with MIPI

Is there any ideas to help me go on?

Thank you very much.

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Contributor IV

I have got this worked.

whe  i set the AXI_CLK_ROOT clock to 528Mhz,(default 264Mhz),

2560x1440@30fps is worked fine.

So it seems that the "ccm_pixel_clk" is not enough in CSI2IPU moudle or MIPI core.

Is there anyone know where can i get detail information about this in freescale documents.

Than kyou.

View solution in original post

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Contributor III

Hi,

I have a similar problem with a custom camera

Can you tell me where you set the AXI_CLK_ROOT to 528 MHz?

Thanks.

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Contributor IV

Set CCM_CBCDR:axi_podf = 0 (divided by 1)

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NXP Employee
NXP Employee

Please also try the following changes:

diff -aur x_imx_kernel_01.01.0.13_orig/kernels/linux-imx6//arch/arm/mach-mx6/clock.c x_imx_kernel_01.01.0.13_pixclk_fix/kernels/linux-imx6//arch/arm/mach-mx6/clock.c

--- x_imx_kernel_01.01.0.13_orig/kernels/linux-imx6//arch/arm/mach-mx6/clock.c 2013-02-26 17:08:42.000000000 -0600

+++ x_imx_kernel_01.01.0.13_pixclk_fix/kernels/linux-imx6//arch/arm/mach-mx6/clock.c 2013-04-26 08:19:08.277962839 -0500

@@ -3900,8 +3900,8 @@

int mux;

u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;

- mux = getmux6(parent, &axi_clk, &pll3_usb_otg_main_clk,

- &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);

+ mux = getmux6(parent, &pll2_pfd_400M, &pll3_usb_otg_main_clk,

+ &axi_clk, &pll2_pfd_352M, NULL, NULL);

reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);

__raw_writel(reg, MXC_CCM_CSCMR1);

@@ -3913,8 +3913,8 @@

u32 reg, div;

reg = __raw_readl(MXC_CCM_CSCMR1);

- div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>

- MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;

+ div = (((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>

+ MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)^0x6 ) + 1;

return clk_get_rate(clk->parent) / div;

}

@@ -5432,7 +5432,7 @@

clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);

clk_set_parent(&emi_clk, &pll2_pfd_400M);

- clk_set_rate(&emi_clk, 200000000);

+ clk_set_rate(&emi_clk, 176000000);

/*

  • on mx6dl, 2d core clock sources from 3d shader core clock,

Best Regards

Lily Zhang

Freescale MPU Support

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Contributor III

Hi xiaoli.zhang‌:

My BSP version is imx_4.1.15_2.0.0_ga .

I can not find your modifications.

Could you explain Why you modified this ?

Could this modified increase mipi-csi2 RX ability over 800Mbs/Lane with 4-Lanes?

Best Regard

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Contributor IV

Hi Zhang,

Can you explain your settings to the clock.c ?

I can't find the relationship between emi_clk and ccm_pixel_clk.

Thank you

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NXP Employee
NXP Employee

EMI change is for one fix during debug.

Best Regards

Lily Zhang

Freescale MPU Support

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Contributor IV

Hi zhang,

Thanks for your reply.

And i tried your changes to emi clock, it worked !

I want know the reasons of this. And what's the recommend way to solve my problem.

changes with axi_clk_root? or your changes with emi_clock ?

Because i must explain it to my customer. And i can't get this clear  from freescale's document.

Thank you!

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NXP Employee
NXP Employee

One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2

interface. The maximum bandwidth of the interface is as follows:

• 400MByte/sec for four data lanes configuration (800Mbps/lane)

• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)

• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)

• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)


For 2560x1440@30fps, the required bandwidth is 2560x1440x30x1.35 (Blanking interval) * DF (data format, defines the number of cycles needed to send a single pixel.). Assume you are using YUV422, 2560x1440x30x1.35x2 = 299M. Still in the bandwidth scope.


Suggest that you can check the detailed data flow and share the detailed failure log for the analysis.

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Contributor IV

Hi zhang,

Thank you so much to reply me.

DF is not 1 ? Yes i am using YUV422 input.

In RM IPU part, there is "• YUV422 = 1 cycle/pixel" about mipi camera interface.

And MIPI can use 4 channels or only 1 channel to send data, So here:

• 400MByte/sec for four data lanes configuration (800Mbps/lane)

This 400MByte is for 4 channels or for 1 channel?

Because I think it will support fast data rate to use 4 channels than 1 channel.

0 channel -----> IPU1 CSI0

1 channel------->IPU1 CSI1

2 channel------->IPU2 CSI0

3 channel------->IPU2 CSI1


Thank you.

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NXP Employee
NXP Employee

Data format examples:

• YUV422 over 16 bit = 1 cycles/pixel

• RGB888 over 8 bit = 3 cycles/pixel

• RGB565 over 16 bit = 2 cycles/pixel

• Bayer/Generic data = 1 cycle/pixel

• YUV422 over 8 bit = 2 cycles/pixel

• BT.656, YUV422 format = 2 cycles/pixel

• BT.1120, YUV422 format = 1 cycle/pixel

This 400MByte is for 4 lanes.

Best Regards

Lily Zhang

Freescale MPU Support

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Contributor IV

Sorry to confuse you.

I mean the virtual channel, not the lanes.

You can use one data lane to send 4 channel data.

or use 4 data lanes to send 1 channel data.

My camera is use 4 data lanes to send 1 channel data.(channel 0 to CSI0 of IPU1)

In chapter 19 (CSI2IPU), there is a virtual channel graph for i.mx6.

Thank you.

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Contributor I

Hi Gao,


I am facing in camera capture on imx6q customize board.

Could you please help me on resolving the issue.


Below are the detail


We are using omnivison ov9740 sensor chip & interface is mipi. We have only one mipi camera device in our customize board.
In our case sensor is sending data in one lane only of mipi.

We are getting “ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0”.

We have checked by putting debug print in mxc_v4l2_capture.c , mxc_mipi_csi2.c & ipu_prp_enc.c.

The camera image setting looks fine i.e(width(1280), height(720), pixformat(UYVY) ,DATA_WIDTH 8bit by debug print in mxc_v4l2_capture.c as well as in sensor file).

The mipi register values are

MIPI_CSI_PHY_STATE 0x320
MIPI_CSI_ERR1 0x0
MIPI_CSI_ERR2 0x1

The board config file setting for mipi,v4l2capture & sensor are below.

1)mipi

static struct mipi_csi2_platform_data mipi_csi2_pdata = {
  .ipu_id = 0,
  .csi_id = 1,
  .v_channel = 0,
  .lanes = 2,
  .dphy_clk = "mipi_pllref_clk",
  .pixel_clk = "emi_clk",
};

2)v4l2_capture
static struct fsl_mxc_capture_platform_data capture_data[] = {
  {
  .csi = 0,
  .ipu = 0,
  .mclk_source = 0,
  .is_mipi = 0,
  }, {
  .csi = 1,
  .ipu = 0,
  .mclk_source = 0,
  .is_mipi = 1,
  },
};

3)ov9740 sensor
static struct fsl_mxc_camera_platform_data mipi_csi2_data = {
  .mclk = 24000000,
  .mclk_source = 0,
  .csi = 1,
  .io_init = mx6q_mipi_sensor_io_init,
  .pwdn = mx6q_mipi_powerdown,
}

Kindly let us know what may be the cause of this error & is there any setting wrong.(specially highlighted variable i.e .csi ,.csi_id).

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Contributor IV

Hi,

Are you using only on data lane of mipi?

but you set “.lanes = 2” in mipi_csi2_pdata.

And from the MIPI_CSI_PHY_STATE=0x320, this means there is data signal only on data lane 1 ,

But not data lane 0.

Can you set your camera to use data lane0 to send data?

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Contributor I

Hi Gao,

I have set  data lane 0 & set “.lanes = 1” in mipi_csi2_pdata.

Still getting same error "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0”.

Below are the log

MIPI_CSI_PHY_STATE value 0x310,0x300,0x300,0x300,0x310,0x310,0x300........ checking at interval of 10milisec

MIPI_CSI_ERR2 value 0x0,0x0,0x10,0x10,0x10,0x0,0x10,0x10,0x10,0x0,0x10 .... checking at interval of 10milisec

Our Mipi sensor clock is  304Mhz.

I am not clear about the Imx-6 MIPI controller clock setting.

Are we suppose to do any change in clock of iMx-6 mipi, if sensor o/p clock get change ?

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Contributor IV

Hi

If MIPI_CSI_PHY_STATE = 0x310 or 0x300, it seems that MIPI module is working.

But I really don’t know about the MIPI_CSI_ERR2.

Another people named wang in community may be help you.

And another thing,

If your virtual channel=0, you should use CSI0 of IPU1

If your virtual channel=1, you should use CSI1 of IPU1

Did you set this correct?

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