imx6q: porting 4.2.2 to 5.1.1 problem with HDMI and lvds display

[Ikal]

Hi folks.

I'm trying to port our board based on Freescale imx.6q from Android Jellybean to Lollipop.

(Linux version 3.0.35 without devicetree -> Linux version 3.14.38 with devicetree).

The board has a main display with 1280x800 pixels connected to lvds0 configured at IPU1.

Further on a HDMI display can be connected via Mini-HDMI-plug configured at IPU0.

A camera ov9740 is connected via MIPI configured to IPU0, too.

With Android 4.2.2 everything works fine.

With Android 5.1.1 I stepped into some trouble...

1.) Problem:

When connecting a HDMI display (1680x1050) via HDMItoDVI cable the main display fails (only stripes will be shown anymore).

At the HDMI display an image will be shown shortly. That’s all.

This could be solved by adding this lines to the devicetree

&clks {

    fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;

};

So, this might be solved.

2.) Problem:

The output to the HDMI device only works fine when using VGA resolution.

Otherwise using higher resolutions the output is shown correctly at HDMI and at the main display first.

But then when e.g. swiping over the touch or modifying content of the display in another way

the main display slows down and the HDMI device gets no signal anymore.

This messages pops up:

imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x00080000

imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_5 = 0x00800000

and from framebuffer used by HDMI:

mxc_sdc_fb fb.26: timeout when waiting for flip irq

Resolutions greater than VGA requires a higher clock, so I assume the clocktree may not be configured correctly.

Different configurations have been tried with no success..

Any help is really appreciated! Any ideas?

Kr, Ingo

When changing CCM_CHSCCDR

from 0x00012080 to 0x00012088

via devregs 0x020C4034 0x00012088

the display on the HDMI monitor appears, but it is overclocked.

Our configuration:

kernel cmd line:

video=mxcfb0:dev=ldb,bpp=32

video=mxcfb1:dev=hdmi,bpp=32

video=mxcfb2:off

video=mxcfb3:off

The only_cea parameter is set to 0.

The chip revision is 0x6315. (IMX_CHIP_REVISION_1_5)

This is our devicetree.

&clks {

    fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;

};

&ldb {

    status = "okay";

    ext-ref;

    lvds-channel@0 {

        crtc = "ipu2-di0";

        fsl,data-mapping = "spwg";    /* spwg or jeida (jeida only with 24bit) */

        fsl,data-width = <24>;

        status = "okay";

        primary;

        display-timings {

            native-mode = <&timing0>;

            timing0: lp101wx1 {

                clock-frequency = <83500000>;

                hactive = <1280>;

                vactive = <800>;

                hback-porch = <200>;

                hfront-porch = <72>;

                vback-porch = <3>;

                vfront-porch = <22>;

                hsync-len = <128>;

                vsync-len = <6>;

                vsync-active = <1>;

            };

        };

    };

};

lvds_display: fb@0 {

    compatible = "fsl,mxc_sdc_fb";

    disp_dev = "ldb";

    interface_pix_fmt = "RGB24";

    default_bpp = <32>;

    int_clk = <0>;

    late_init = <0>;

    status = "disabled";

};

hdmi_display: fb@1 {

    compatible = "fsl,mxc_sdc_fb";

    disp_dev = "hdmi";

    interface_pix_fmt = "RGB24";

    mode_str ="1920x1080M@60";

    default_bpp = <32>;

    int_clk = <0>;

    late_init = <0>;

    status = "disabled";

};

&dcic1 {

    dcic_id = <0>;

    dcic_mux = "dcic-hdmi";

    status = "okay";

};

&dcic2 {

    dcic_id = <1>;

    dcic_mux = "dcic-lvds0";

    status = "okay";

};

&hdmi_core {

    ipu_id = <0>;

    disp_id = <0>;

    status = "okay";

};

ipu_1: ipu@02400000 {

    compatible = "fsl,imx6q-ipu";

    reg = <0x02400000 0x400000>;

    interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,

                    <0 5 IRQ_TYPE_LEVEL_HIGH>;

    clocks = <&clks IMX6QDL_CLK_IPU1>,

            <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,

            <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,

            <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,

            <&clks IMX6QDL_CLK_PRG0_APB>;

    clock-names = "bus",

                "di0", "di1",

                "di0_sel", "di1_sel",

                "ldb_di0", "ldb_di1", "prg";

    resets = <&src 2>;

    bypass_reset = <0>;

};

ipu_2: ipu@02800000 {

    compatible = "fsl,imx6q-ipu";

    reg = <0x02800000 0x400000>;

    interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,

                <0 7 IRQ_TYPE_LEVEL_HIGH>;

    clocks = <&clks IMX6QDL_CLK_IPU2>,

            <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,

            <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,

            <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;

    clock-names = "bus",

                "di0", "di1",

                "di0_sel", "di1_sel",

                "ldb_di0", "ldb_di1";

    resets = <&src 4>;

    bypass_reset = <0>;

};

Some outputs:

Without HDMI: main display works.

DC stop timeout - 0 * 10ms

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:1, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu2_pclk0_div<

ipu1_di0 read BS_CLKGEN0 div:16, final_rate:1357714272, prate:84857142

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:1, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu2_pclk0_div<

ipu1_di0 read BS_CLKGEN0 div:16, final_rate:1357714272, prate:84857142

panel size = 1280 x 800

pixel clk = 83500000

---*---> ipu_init_sync_panel() in line:1172, ldb 0 clk:>ldb_di0< :84857142

---*---> ipu_init_sync_panel() in line:1173, ldb 1 clk:>ldb_di1< :10592857

---*---> ipu_init_sync_panel() in line:1174, pixel_clk[0]:>ipu2_pclk_0< :84857142

---*---> ipu_init_sync_panel() in line:1175, pixel_clk[0]:>ipu2_pclk0_sel< :84857142

---*---> ipu_init_sync_panel() in line:1176, parent clk:>ldb_di0< :84857142

---*---> ipu_init_sync_panel() in line:1177, di_clk[0]:>ipu2_di0< :84857142

---*---> ipu_init_sync_panel() in line:1178, ipu->ipu_clk:>ipu2< :264000000

use special clk parent

round pixel clk:84857142

---*---> ipu_init_sync_panel() in line:1243, pixel_clk[0]:>ipu2_pclk0_sel< :84857142 / 84857142

div:1

---*---> ipu_init_sync_panel() in line:1517, sig.interlaced:0x0

---*---> ipu_init_sync_panel() in line:1623, sig.Vsync_pol:0x1

---*---> ipu_init_sync_panel() in line:1639, DI_GENERAL:0x300004

DMFC high resolution has set, will not change

With HDMI connected: main display slows down, HDMI shows som frames then black

panel size = 1680 x 1050

pixel clk = 146262000

---*---> ipu_init_sync_panel() in line:1172, ldb 0 clk:>ldb_di0_div_sel< :84857142

---*---> ipu_init_sync_panel() in line:1173, ldb 1 clk:>ldb_di1_div_sel< :10592857

---*---> ipu_init_sync_panel() in line:1174, pixel_clk[0]:>ipu1_pclk_0< :0

---*---> ipu_init_sync_panel() in line:1175, pixel_clk[0]:>ipu1_pclk0_sel< :264000000

---*---> ipu_init_sync_panel() in line:1176, parent clk:>ipu1_di0_pre< :24716667

---*---> ipu_init_sync_panel() in line:1177, di_clk[0]:>ipu1_di0< :24716667

---*---> ipu_init_sync_panel() in line:1178, ipu->ipu_clk:>ipu1< :264000000

try ipu internal clk

rounded pix clk:176000000

try ipu ext di clk

---*---> ipu_init_sync_panel() in line:1213, clk:>ipu1_di0<,146262000

di clk:146262000

---*---> ipu_init_sync_panel() in line:1223, pixel_clk[0]:>ipu1_pclk0_sel< :264000000

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:0, final_rate:2340192000, prate:146262000

ipu_pixel_clk: ipu:0, di:0, di_clk_ext:0x100000, di_gen reg:0x300000, index:1.

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:0, final_rate:2340192000, prate:146262000

round pixel clk:146262000

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:16, final_rate:2340192000, prate:146262000

---*---> ipu_init_sync_panel() in line:1243, pixel_clk[0]:>ipu1_pclk0_sel< :146262000 / 146262000

div:1

---*---> ipu_init_sync_panel() in line:1517, sig.interlaced:0x0

---*---> ipu_init_sync_panel() in line:1617, sig.Hsync_pol:0x1

---*---> ipu_init_sync_panel() in line:1639, DI_GENERAL:0x300002

DMFC high resolution has set, will not change

DC stop timeout - 0 * 10ms

panel size = 1680 x 1050

pixel clk = 146262000

---*---> ipu_init_sync_panel() in line:1172, ldb 0 clk:>ldb_di0_div_sel< :84857142

---*---> ipu_init_sync_panel() in line:1173, ldb 1 clk:>ldb_di1_div_sel< :20894571

---*---> ipu_init_sync_panel() in line:1174, pixel_clk[0]:>ipu1_pclk_0< :146262000

---*---> ipu_init_sync_panel() in line:1175, pixel_clk[0]:>ipu1_pclk0_sel< :146262000

---*---> ipu_init_sync_panel() in line:1176, parent clk:>ipu1_di0_pre< :146262000

---*---> ipu_init_sync_panel() in line:1177, di_clk[0]:>ipu1_di0< :146262000

---*---> ipu_init_sync_panel() in line:1178, ipu->ipu_clk:>ipu1< :264000000

try ipu internal clk

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:16, final_rate:4224000000, prate:264000000

ipu_pixel_clk: ipu:0, di:0, di_clk_ext:0x0, di_gen reg:0x200002, index:0.

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:16, final_rate:4224000000, prate:264000000

rounded pix clk:176000000

try ipu ext di clk

---*---> ipu_init_sync_panel() in line:1213, clk:>ipu1_di0<,146262000

di clk:146262000

---*---> ipu_init_sync_panel() in line:1223, pixel_clk[0]:>ipu1_pclk0_sel< :264000000

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:16, final_rate:2340192000, prate:146262000

ipu_pixel_clk: ipu:0, di:0, di_clk_ext:0x100000, di_gen reg:0x300002, index:1.

---*---> _ipu_pixel_clk_div_recalc_rate() in line:154, ipu:0, di:0, flags:0x0

---*---> _ipu_pixel_clk_div_recalc_rate() in line:155, hw clk:>ipu1_pclk0_div<

ipu0_di0 read BS_CLKGEN0 div:16, final_rate:2340192000, prate:146262000

round pixel clk:146262000

---*---> ipu_init_sync_panel() in line:1243, pixel_clk[0]:>ipu1_pclk0_sel< :146262000 / 146262000

div:1

---*---> ipu_init_sync_panel() in line:1517, sig.interlaced:0x0

---*---> ipu_init_sync_panel() in line:1617, sig.Hsync_pol:0x1

---*---> ipu_init_sync_panel() in line:1639, DI_GENERAL:0x300002

DMFC high resolution has set, will not change

imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x00080000

imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_5 = 0x00800000

mxc_sdc_fb fb.26: timeout when waiting for flip irq

[alejandrolozan1]

Hi,

Have you verified that the HDMI in the original Android Lollippo L3.14.38 is working as expected?

This seems to be a clock issue, is there a way you can check with a FSL board?

When you change CCM_CHSCCDR from 0x00012080 to 0x00012088 you are  increasing the divisor.

Can you verify the frequency in the CCM_CLKO1 of the corresponding ipuX_di_clkX_root?

Best Regards,

Alejandro

[Ikal · Accepted solution]

Hi Alejandro.

Thanksfor your reply.

Today, early in the morning I got it running!

These lines have been missing, in the old kernel it was done by post_ cpu_init()

__raw_writel(IOMUXC_GPR6_IPU1_QOS, IOMUXC_GPR6);

__raw_writel(IOMUXC_GPR7_IPU2_QOS, IOMUXC_GPR7);

What about the other code inside this function regarding GPR4, VPU caching – is it also needed?

With Best Regards,

Ingo