imx6q PCIE_PHY_ATEOVRD register definition correct?

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imx6q PCIE_PHY_ATEOVRD register definition correct?

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martinkepplinge
Contributor I

There are pages like https://community.nxp.com/docs/DOC-334667  that use imx6q's PCIE_PHY_ATEOVRD register bits not as described in the Reference Manual (REV 4). Instead, they use the register's bits shited to the right by 1. Could you clarify? Thanks a lot!

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 

  Section 49.7 (Control Memory Map/Register Definition) of the i.MX6 D/Q Reference Manual contains

PCIe PHY registers description. According to the note in the section beginning : “PCIe PHY is not memory

mapped to processor address space, so the absolute addresses shown is the relative address and is not valid”.

Also, note, the PCIe chapters of the i.MX6 Reference Manual are based on IP specs and information, provided there,

are restricted by (third party) agreement.

 

  You may look at C-functions pcie_phy_cr_read() and pcie_phy_cr_write() of the Platform SDK or Linux BSP

sources - how to access the PCIe PHY registers.

 

The Platform SDK is not supported more, nevertheless, You may try the following, in order to get its sources.

 

swp-report/iMX6_Platform_SDK at master · backenklee/swp-report · GitHub 


Have a great day,
Yuri

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