imx6d LVDS 1920x1080 (split mode on uboot)

cancel
Showing results for 
Search instead for 
Did you mean: 

imx6d LVDS 1920x1080 (split mode on uboot)

Jump to solution
521 Views
Contributor II

I have a custom board  with imx6d working fine with linux & android  (4.1.15 , 6.01 )

I have a fast  splash screen  on uboot , with the old display (1024x800 rgb24 single ch lvds) was ok, but with the new panel at 1920x1080 ( after some changes at setup_display function  )  display the  splash screen in dual channel lvds mode but the X resolution is 'virtual' , only 960 pixel are drawing in the lvds. The Y resolution is OK at 1080. Colors and bitmap image(dual width) is OK.

On uboot I could not make a proper debug of IPU registers. Please, someone can  send an example of function to RW a IPUx register on uboot.


Thanks

Labels (2)
0 Kudos
1 Solution
35 Views
Contributor II

I have solved.

On split mode LDB_DIx_IPU_DIV on CCM_CSCMR2 must be the half ,(divider to 3,5)

On function setup_display_clock :

        reg = readl(&mxc_ccm->cscmr2);
        reg &=~(MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
/*      reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
*/
        writel(reg, &mxc_ccm->cscmr2);

On function setup_display:

       int reg;
        reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
             |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
             |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
             |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
             |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
#ifdef CONFIG_FORM_500
/* split_mode */
             |IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
             |IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
             |IOMUXC_GPR2_SPLIT_MODE_EN_MASK
             |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
#else
             |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
             |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
             |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
#endif
             |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;

       writel(reg, &iomux->gpr[2]);

that's all.

View solution in original post

1 Reply
36 Views
Contributor II

I have solved.

On split mode LDB_DIx_IPU_DIV on CCM_CSCMR2 must be the half ,(divider to 3,5)

On function setup_display_clock :

        reg = readl(&mxc_ccm->cscmr2);
        reg &=~(MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
/*      reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
*/
        writel(reg, &mxc_ccm->cscmr2);

On function setup_display:

       int reg;
        reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
             |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
             |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
             |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
             |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
#ifdef CONFIG_FORM_500
/* split_mode */
             |IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
             |IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
             |IOMUXC_GPR2_SPLIT_MODE_EN_MASK
             |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
#else
             |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
             |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
             |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
#endif
             |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;

       writel(reg, &iomux->gpr[2]);

that's all.

View solution in original post