imx6 uboot and cache

[vsiles]

Hi !

I'm working with several flavor of imx6 boards (sabre sd from NXP, sabre_lite from boundary devices) and we are running a secure OS in Trustzone, alongside Linux in the normal world. Our current configuration does not configure the PL310 L2 cache controller and does not set the ACTLR.SMP bit at boot. We wait for Linux to start and requests these actions (the first one to the monitor, for secure access, the second one it can do by itself).

Now I am trying to activate the PL310 during our boot sequence. The whole boot sequence is as follows:

1) U-Boot SPL loads the secure kernel and U-Boot from an SD card, and copy them to RAM

2) execution is given to the secure kernel which configures the secure world (Secure MMU is activated)

3) at some point, we give back the execution to the normal world (to U-boot, I think it activates an MMU, but there is no PL310 related code executed)

4) U-boot loads Linux from the SD card and launch it

My current status is quite buggy and random, but it seems that activating the PL310 or the ACTLR bit before U-boot (the second one, in the normal world) prevent it to work (most of the time, it fails to configure the SD controller to load Linux).

Any idea why activating PL310 or ACTLR.SMP before uboot is started might introduce cache issue ?

[Yuri]

Hello,

Please check Your design regarding SMP mode in the recent Errata.

http://www.nxp.com/files/32bit/doc/errata/IMX6DQCE.pdf

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[vsiles]

Thank you for the answer YuriMuhin_ng‌.

I already checked the errata (but I might have missed some, I'll double check).

The strange thing is that I'm running only on core 0 at the moment, the 3 other cores are still on hold. My goal is to correctly set the ACTLR & SCU for core 0 before releasing the other cores. So far, I managed to enable the PL310 in a single core scenario, with ACTLR.SMP & SCU disabled.

From this state, here is what I'm doing at the moment (and it's not working...):

- MMU is off, PL310 is disabled, L1 I / D cache are off

- invalidate all L1 D cache by set/way + dsb isb

- write in the undocumented diagnostic register for errata of imx6 (bits 4, 6, 11, 21)

- write in the undocument SCU register for errata (SCU_BASE_PA + 0x30, bit 0)

- invalidate SCU tags by writing 0xffff in the invalidate register

- enable the SCU (setting ENABLE & STANDBY_ENABLE bit in the contrl register)

- dmb

- set the ACTLR.SMP and ACTLR.FW bits

- set TTBR0/1 TTBCR

- invalidate I cache + dsb isb

- set SCTLR (configuration activates I cache, D cache & MMU at the same time, + other bits)

- isb

The configuration / activation of PL310 is done after this, with MMU on.

Am I missing something ? Am I doing something wrong to enable SCU & ACTLR ?