imx6 solo power up sequence, leakage from peripheral

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imx6 solo power up sequence, leakage from peripheral

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diegoperez
Contributor II

Hi,


Power sequence specifications at "IMX6SDLCEC 4.2.1 Power-Up Sequence” says:


“Ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies).”

I have +3v3 that is the first power to supplying VDD_SNVS_IN and VDD_HIGHT_IN. To prevent this “back voltage” I power all 3,3V peripheric and NVCC_x through a power switch. When this power switch is off (power up sequence is going), I have some mV in peripheric (around 10mv).


I think 10mv is a very low voltage to produce a latch-up or something like that, but I launch the question. Is it safe the power up sequence with 10mv in 3v3v peripherals?

BR

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Diego

I think you are right, 10mv is too small to be considered as violation power-up sequence.

Best regards
igor
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