imx6 ddr fly-by topology

[priyaprasad]

In the hardware design guidelines of IMX6Q it is mentioned that Add/CMD/CTL has to be length matched with clock signals. IMX6 DDR controller is having 2 clocks (Dram_sdclk0, Dram_sdclk1)each is given to two DDR's. We are facing a problem of length matching the clock's(Dram_sdclk0, Dram_sdclk1) to Address and command and control signals as we are routing ddr signal in fly by topology . So, we are using only one Dram_sdclk0 signal for all the four DDR's and terminating the second clock at the processor. Please suggest any changes required and recommendation about ddr address signal maximum  possible length and about matching specific to fly by topology.

Regards

Priya

[Yuri]

Hello,

  According to the i.MX6 Design Checklist, it is suggested to use "T" topology
when the number of DDR3 chips are not more than four.  Otherwise "Fly-by"
topology is recommended, since it allows to decrease timing / trace length
requirements, but  additional calibration procedures must be performed.

Please use

i.MX6/7 DDR Stress Test Tool V2.60 

Freescale i.MX6 DRAM Port Application Guide-DDR3 

Have a great day,

Yuri

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[priyaprasad]

We have routed DDR3 address and command lines as per fly by topology in our design . Do we need to make any changes in u-boot and OS files due to this modification, or the same file used for same size DDR3 board but with T - topology can be used. 

Thanks

Regards

Priya

[weivivien]

hello, our team also design four DDR3 chips with fly-by topology, we are confused about can we use two clk each for two DDR(just like reference design ). so we wondering can we use one clock for four DDR chips. did your board running properly?

we are hoping for you reply!

vivien

[priyaprasad]

Hi vivien

We have used only one clock for four DDR chips in fly by topology and our board is running fine. Only thing we had to do DDR calibration.