Hello together,
for a customer project we want to use a PCM5310 audio codec from TI . Unfortunatlly ther is no driver availible. So we had to write our own SOC driver for this codec. Especially the I2S bus is a problem
The big question is the masterclock for the I2S bus of the codec According the data sheet for the codec it should be for 48kHz sampling frequency 12.288MHz or 24.5760 or 36.864 MHz. For a sampling frequency of 44,1kHz it should be 11,2896MHz or 22,5792MHz.
We use GPIO 05 (Pad R4) which could be used as a clock signal routed to the Audio PLL4 for the master clock. Therefore we want to connect it to this PLL. So the question is, how we should set this PLL and the dividers to get one of the necessary frequencies. I read into the cklock chapter of the imx6 spec and had the idea to change the frequency of the PLL from 650MHz up to 1104MHz, by change the factor for the PLL from 27 to 46. If I dived this by 30, I get a frequency of 36,80MHz which means a divergence of 0.2%
The question is now. Is this a correct idea and if yes, how can I program it. My idea is, that I have to make changes inside clock.c
regards Gerhard
