First, many thanks for the quick answer!
As usual, I think it's essential to get the details correctly, so some more detailed questions:
1. While the question in this thread is specific to PLLv3, the answers apply to all PLLs, correct? I.e. we have to do the same for PLLv1, PLLv2 etc, correct?
2. I have some difficulty to match the section 18.5.1.5.3 PLL clock change - "Before changing the PLL setting, power it down. Power up the PLL after the change" to the register bits of the CCM_ANALOG_PLL_xxx registers. The CCM_ANALOG_PLL_xxx registers have 3 bits which seem to be involved in our discussion:
So the correct sequence to change the PLL rate is
a) Put the PLL in BYPASS by setting the BYPASS bit CCM_ANALOG_PLL_xxx[16] = 1 (or ensure in different way that the peripherals are not driven by the PLL clock we are switching, e.g. by disabling them or switching them to an other clock source)
b) Powerdown the PLL by setting the POWERDOWN bit CCM_ANALOG_PLL_xxx[12] = 1
c) Change the dividers
d) Powerup the PLL by setting the POWERDOWN bit CCM_ANALOG_PLL_xxx[12] = 0
e) Wait for lock (then the clock is stable)
f) Remove the BYPASS by setting the BYPASS bit CCM_ANALOG_PLL_xxx[16] = 0 (feed the peripherals with the new clock)
And while doing this, don't touch the ENABLE bit, i.e. keep the PLL enabled by CCM_ANALOG_PLL_xxx[13] = 1
Is this sequence correct?
3. In the recent FSL BSP the before changing the clock, the bypass is explicitly removed:
linux-2.6-imx.git - Freescale i.MX Linux Tree
Wouldn't this result in any clock glitch? Even if you reset afterwards?
