imx515 jtag jlink debug error

[taotaoxx]

Tue Oct 25, 2022 10:51:32: IAR Embedded Workbench 9.10.2 (D:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armPROC.dll)
Tue Oct 25, 2022 10:51:33: Loaded macro file: E:\work\imx51\imx51-jtag\arm\9.10.2\NXP\MX51\IMX51_EVK\GettingStarted\config\mcimx51evk_ddr2.mac
Tue Oct 25, 2022 10:51:33: JLINK command: ProjectFile = E:\work\imx51\imx51-jtag\arm\9.10.2\NXP\MX51\IMX51_EVK\GettingStarted\settings\GettingStarted_DDR_DEBUG.jlink, return = 0
Tue Oct 25, 2022 10:51:33: Device "IMX516" selected.
Tue Oct 25, 2022 10:51:33: DLL version: V7.20a, compiled May 7 2021 16:52:52
Tue Oct 25, 2022 10:51:33: Firmware: J-Link V9 compiled May 7 2021 16:26:12
Tue Oct 25, 2022 10:51:34: JTAG speed is initially set to: 32 kHz
Tue Oct 25, 2022 10:51:34: Software reset was performed
Tue Oct 25, 2022 10:51:34: Initial reset was performed
Tue Oct 25, 2022 10:51:34: TotalIRLen = 13, IRPrint = 0x0101
Tue Oct 25, 2022 10:51:34: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
Tue Oct 25, 2022 10:51:34: JTAG chain detection found 3 devices:
Tue Oct 25, 2022 10:51:34: #0 Id: 0x1BA00477, IRLen: 04, CoreSight JTAG-DP
Tue Oct 25, 2022 10:51:34: #1 Id: 0x00000001, IRLen: ?, Unknown device
Tue Oct 25, 2022 10:51:34: #2 Id: 0x1190C01D, IRLen: ?, Unknown device
Tue Oct 25, 2022 10:51:34: DPv0 detected
Tue Oct 25, 2022 10:51:34: Scanning AP map to find all available APs
Tue Oct 25, 2022 10:51:34: AP[3]: Stopped AP scan as end of AP map has been reached
Tue Oct 25, 2022 10:51:34: AP[0]: AHB-AP (IDR: 0x14770001)
Tue Oct 25, 2022 10:51:34: AP[1]: APB-AP (IDR: 0x04770002)
Tue Oct 25, 2022 10:51:34: AP[2]: JTAG-AP (IDR: 0x14760010)
Tue Oct 25, 2022 10:51:34: Iterating through AP map to find APB-AP to use
Tue Oct 25, 2022 10:51:34: AP[0]: Skipped. Not an APB-AP
Tue Oct 25, 2022 10:51:34: AP[1]: APB-AP found
Tue Oct 25, 2022 10:51:34: Invalid ROM table component ID 0x00000000 @ 0x80000FF0 (expected 0xB105100D). Trying again at alternative offset.
Tue Oct 25, 2022 10:51:34: ROMTbl[0][0]: CompAddr: 60001000 CID: B105900D, PID: 000BB907 ETB
Tue Oct 25, 2022 10:51:34: ROMTbl[0][1]: CompAddr: 60002000 CID: B105900D, PID: 104BB921 ???
Tue Oct 25, 2022 10:51:34: ROMTbl[0][2]: CompAddr: 60003000 CID: B105900D, PID: 004BB912 TPIU
Tue Oct 25, 2022 10:51:34: ROMTbl[0][3]: CompAddr: 60004000 CID: B105900D, PID: 104BB922 ???
Tue Oct 25, 2022 10:51:34: ROMTbl[0][4]: CompAddr: 60005000 CID: B105900D, PID: 000BB906 CTI
Tue Oct 25, 2022 10:51:34: ROMTbl[0][5]: CompAddr: 60006000 CID: B105900D, PID: 000BB906 CTI
Tue Oct 25, 2022 10:51:34: ROMTbl[0][6]: CompAddr: 60007000 CID: B105900D, PID: 000BB906 CTI
Tue Oct 25, 2022 10:51:34: ROMTbl[0][7]: CompAddr: 60008000 CID: B105900D, PID: 104BBC08 Cortex-A8
Tue Oct 25, 2022 10:51:34: Found Cortex-A8 r2p5
Tue Oct 25, 2022 10:51:34: 6 code breakpoints, 2 data breakpoints
Tue Oct 25, 2022 10:51:34: Debug architecture ARMv7.0
Tue Oct 25, 2022 10:51:34: Data endian: little
Tue Oct 25, 2022 10:51:35: Main ID register: 0x412FC085
Tue Oct 25, 2022 10:51:35: I-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
Tue Oct 25, 2022 10:51:35: D-Cache L1: 32 KB, 128 Sets, 64 Bytes/Line, 4-Way
Tue Oct 25, 2022 10:51:35: Unified-Cache L2: 256 KB, 512 Sets, 64 Bytes/Line, 8-Way
Tue Oct 25, 2022 10:51:35: System control register:
Tue Oct 25, 2022 10:51:35: Instruction endian: little
Tue Oct 25, 2022 10:51:35: Level-1 instruction cache disabled
Tue Oct 25, 2022 10:51:35: Level-1 data cache disabled
Tue Oct 25, 2022 10:51:35: MMU disabled
Tue Oct 25, 2022 10:51:35: Branch prediction disabled
Tue Oct 25, 2022 10:51:35: Found 3 JTAG devices, Total IRLen = 13:
Tue Oct 25, 2022 10:51:35: #0 Id: 0x1BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Oct 25, 2022 10:51:35: #1 Id: 0x00000001
Tue Oct 25, 2022 10:51:35: #2 Id: 0x1190C01D
Tue Oct 25, 2022 10:51:36: Disabling MMU...
Tue Oct 25, 2022 10:51:36: Configuring Clocks...
Tue Oct 25, 2022 10:51:37: Configuring DDR...
Tue Oct 25, 2022 10:51:40: Loaded debugee: E:\work\imx51\imx51-jtag\arm\9.10.2\NXP\MX51\IMX51_EVK\GettingStarted\DDR_DEBUG\Exe\GettingStarted.out
Tue Oct 25, 2022 10:51:40: RESET (pin 15) high, but should be low. Please check target hardware.
Tue Oct 25, 2022 10:51:40: Hardware reset with strategy 0 was performed
Tue Oct 25, 2022 10:51:40: Verification error at 0x9000'0003: mem = 0x00, file = 0xE5
Tue Oct 25, 2022 10:51:40: Download completed but verification failed.
Tue Oct 25, 2022 10:51:40: Software reset was performed
Tue Oct 25, 2022 10:51:40: Target reset
Tue Oct 25, 2022 10:51:40: Disabling MMU...
Tue Oct 25, 2022 10:51:40: There were 1 error and 1 warning during the initialization of the debugging session.

[taotaoxx]

Tue Oct 25, 2022 10:51:40: Verification error at 0x9000'0003: mem = 0x00, file = 0xE5，

ddr error？

[Bio_TICFSL]

Hello,

In this case you need go with IAR for debugging errors

Regards