imx28 low Wifi Throughput

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imx28 low Wifi Throughput

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thejay
NXP Employee
NXP Employee

I have large customer who is using the imx28 and the Qualcom/Atheros QCA 6124 wifi module.

They are only seeing about 20MBs using iperf.

They have a bunch of questions I need help with:

  1. Setting of SDIO clock
    1. How
      do we go about setting the SDIO clock ?
    2. Currently
      we see the SDIO clock is set to 48 Mhz, how do we set it to maximum (52Mhz) ?
    3. Let
      us know the changes to be done for the same.
  2. SDR v/s DDR operation
    1. We
      observe in “linux-2.6.35.3\arch\arm\mach-mx28\device.c” DDR capability is
      enabled, i.e. caps has “MMC_CAP_DATA_DDR” bit enabled. (Attached file for
      reference).
    2. Is
      this the only place where the DDR capability needs to be set.
    3. How
      do we verify during transfer if indeed DDR operation is happening ?
  3. SSP2 interface with Wifi
    1. Based
      on discussion with Qualcomm team, DDR mode only applies to memory cards.
    2. How
      does iMX take care of setting the interface in SDR/DDR mode ?
      • If
        you refer to the device.c attached, DDR capability is enabled on SSP2.
  4. Bus clock frequency
    1. We
      captured the Wi-Fi SDIO interface signal on our product using Logic analyzer.
    2. During
      bus active state clock frequency is 48MHz and during bus idle state clock
      frequency reduces to 6MHz. 

Thanks,

Jay

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fabio_estevam
NXP Employee
NXP Employee

Hi Jay,

1. You can set the SDIO clock to 52MHz by doing:

.max_clk    = 48000000, in the mxs_mmc_platform_data structure inside device.c

2. Yes, that's the place where DDR mode is set. You should remove it in the SDIO case

3. Yes, you should remove it. Also, I guess you are operating in 4-bit mode, so MMC_CAP_8_BIT_DATA should also be removed.

Regards,

Fabio Estevam

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fabio_estevam
NXP Employee
NXP Employee

Hi Jay,

1. You can set the SDIO clock to 52MHz by doing:

.max_clk    = 48000000, in the mxs_mmc_platform_data structure inside device.c

2. Yes, that's the place where DDR mode is set. You should remove it in the SDIO case

3. Yes, you should remove it. Also, I guess you are operating in 4-bit mode, so MMC_CAP_8_BIT_DATA should also be removed.

Regards,

Fabio Estevam

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fabio_estevam
NXP Employee
NXP Employee

I meant .max_clk = 52000000 ;-)

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jörg_krause
Contributor III

Hi Fabio,

where can I set this in the mainline kernel?

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fabio_estevam
NXP Employee
NXP Employee

Hi Jörg,

We do not set it directly like in 2.6.35.

Regards,

Fabio Estevam

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jörg_krause
Contributor III

I see! The best matching SDIO clock I can get is 48 MHz. Thanks!

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