We have a custom board where we can't use the DQS pad for flexspi port A, and thus we can only run flash at a max speed of 60 MHz.
In the nor polling SDK example, I made the following changes in system_MIMX1024.c (called from startup code) to accommodate for the 60 MHz requirement.
/* Configure FLEXSPI_A_DQS */
// CHANGE #1: Disabled, we don't have DQS pad available
// IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
/* Disable I cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
/* Re-Configure FLEXSPI NOR via ROM API, for details please refer to the init function of ROM FLEXSPI NOR flash
driver which is in fsl_romapi.h and fsl_romapi.c in the devices\${soc}\drivers directory of SDK package */
uint8_t flexspi_nor_config[512];
memcpy((void *)flexspi_nor_config, (void *)FLASH_CONFIG_ADDRESS, sizeof(flexspi_nor_config));
//flexspi_nor_config[12] = 1U; /* kFLEXSPIReadSampleClk_LoopbackFromDqsPad */
//flexspi_nor_config[70] = 7U; /* kFLEXSPISerialClk_133MHz */
flexspi_nor_config[12] = 0U; /* CHANGE #2: kFLEXSPIReadSampleClk_LoopbackInternally */
flexspi_nor_config[70] = 3U; /* CHANGE #3: kFLEXSPISerialClk_60MHz */
flexspi_nor_init_t flash_init = (flexspi_nor_init_t)ROM_FLASH_INIT_ADDRESS;
flash_init(0U, flexspi_nor_config);
But, I also see that this SDK example configures the FlexSPI clock (app.h, flexspi_clock_init):
/* Switch to PLL2 for XIP to avoid hardfault during re-initialize clock. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Set PLL2 PFD2 clock 396MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */
Can I leave the FlexSPI clock running at 133 MHz when flash is supposed to run at 60 MHz?
Or do I need to reconfigure clocks to get a FlexSPI clock frequency that is exactly 60 MHz?
Does the FlexSPI clock frequency need to correspond with the configured flash speed?
