imx.6, EIM in burst mode, can BCLK be continuous?

[fjeanson]

Hi,

We know that BCM is:

0: The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the burst clock is not running it remains in a logic 0 state.

1 : The burst clock runs whenever ACLK is active (independent of chip select configuration)

why is there this note in the reference manual of imx.6 (rev2, 06/2014) section 22.9.7, p.1073, BCM bit:

"NOTE: This bit should be used only in async. accesses. No sync access can be executed if this bit is set."

I assume "used" means "1", and that "sync access" means SRD and SWR are set to 1.

in other words, can we have BCLK continuous in burst mode?

Thanks, Francis

[dank1]

I tried activating the BCLK continuously on my i.MX6 Dual/Quad by setting ('1') the BCM bit (bit 0) on the EIM_WCR (0x021B_8090h) register.

I am not getting any clock on BLCK - constant '0'.

Did I forget anything?

[Yuri]

  When using an continuous BCLK in synchronous mode, BCD MUST be set to 0.

Please check it.

~Yuri.

[Yuri · Accepted solution]

  The i.MX6 DQ does not have special PLL for providing continuous BCLK, synchronized

with internal (system bus) ACLK. This feature is supported in i.MX6 S/DL. So, for i.MX6 DQ

we cannot guarantee, that BCLK in continuous mode is fully synchronized with ACLK.

This is why it was stated that the  continuous mode is intended mainly for debugging

(under the i.MX6 DQ). Nevertheless,  some customers use it.

  As for i.MX6 S/DL, please take a look at section 22.5.1 (Continuous BCLK) for further

details of the i.MX6 S/DL Reference Manual (IMX6SDLRM, Rev. 1, 04/2013).

Have a great day,
Yuri

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