my assumption is that only a full bank of gpio pins can be assigned to A or M4 side, not a single GPIO pin. Is this correct ?
gpio peripheral module includes bunch of IO pins, usually 32. It is easy to remove whole gpio "bank" from device tree on Linux and use it exclusively on M4. Easy to say, hard to do since it puts serious limits on pin usage. It is big problem NXP should address.
@angelo_d, yes it is "easier" to dedicate whole bank to M4. There's semi-complete driver drivers/gpio/gpio-imx-rpmsg.c, which was introduced in imx7ulp BSP. It is supposed to run on Linux, and corresponding SRTM service is supposed to run on M4. Unfortunately semi-, because it had GPIO interrupts and usage from atomic kernel context incomplete. Perhaps it has changed, I don't know. See attached driver with my mods, which seems working well on imx7d. For SRTM code please look in imx7ulp BSP.