we use KSZ9131 phy on iMX8mq android platform
[ 13.758907] Microchip KSZ9131 Gigabit PHY 30be0000.ethernet-1:00: attached PHY driver [Microchip KSZ9131 Gigabit PHY] (mii_bus:phy_addr=30be0000.ethernet-1:00, irq=POLL)
[ 13.774999] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 13.802886] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 15.812345] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 15.820614] fec 30be0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
vp6820_8mq:/ # ifconfig
eth0 Link encap:Ethernet HWaddr 1c:2e:3d:4e:5f:66 Driver fec
inet6 addr: fe80::b206:dc33:b67b:8af1/64 Scope: Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:14 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 TX bytes:2144
eth0 is up successfully,but cannot get ip address
Do you have any idea?
Hi Joan
according to this thread Porting KSZ9031 to i.MX BSP
Do we need to change clocks as below?
assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
<&clk IMX8MQ_CLK_ENET_REF>,
<&clk IMX8MQ_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS2_PLL_250M>;
in imx8mq_evk.c
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
printf("iomux gpr1 is %u \n",iomuxc_gpr_regs->gpr[1]);
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
//clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
//IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], BIT(13) | BIT(17), 0);
printf("after set iomux gpr1 is %u \n",iomuxc_gpr_regs->gpr[1]);
return set_clk_enet(ENET_125MHZ);
}
it can only set clock to 125MHz
can you help us check?
Thanks
Neil
1) try to set uboot I mentioned firstly, then tell me the result
2) I don't know what schematic you use, this document is for imx7d, you need to refer to the i.mx8mq dts file, did you change the dts file according to your design? if you don't change HW, don't forget set reset pin in your dts, but refer to your log file, it seems you set correct in dts file
3) for imx8mq_evk.c, do you mean set in the uboot? you don't need to change this, for porting KSZ9131 on the imx7d, because the customized board uses GPIO1_IO03 as reset pin, I change the source code like below, maybe you can refer to it, I don't remove the source code, just use "//" as cancellation, this is 4.9.88 source code, you can compare with this
static int setup_fec(int fec_id)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
int ret;
unsigned int gpio;
/*ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio)
if (ret) {
printf("GPIO: 'gpio_spi@0_5' not found\n");
return -ENODEV;
}*///joan
imx_iomux_v3_setup_pad(MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL));//Joan
//imx_iomux_v3_setup_multiple_pads(phy_reset_pads, ARRAY_SIZE(phy_reset_pads));//joan
//ret = gpio_request(gpio, "enet_phy_rst"); joan
ret = gpio_request(IMX_GPIO_NR(1, 3), "enet_phy_rst"); //joan
if (ret && ret != -EBUSY) {
//printf("gpio: requesting pin %u failed\n", gpio); joan
printf("gpio: requesting pin Io03 failed\n"); //joan
return ret;
}
/*gpio_direction_output(gpio, 0);
udelay(500);
gpio_direction_output(gpio, 1);*/ //joan
gpio_direction_output(IMX_GPIO_NR(1, 3), 0); //joan
mdelay(20);//joan
gpio_direction_output(IMX_GPIO_NR(1, 3), 1); //joan
udelay(100);//joan
if (0 == fec_id) {
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
} else {
/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
if (mx7sabre_rev() >= BOARD_REV_B) {
/* On RevB, GPIO1_IO04 is used for ENET2 EN,
* so set its output to low to enable ENET2 signals
*/
gpio_request(IMX_GPIO_NR(1, 4), "fec2_en");
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
}
}
return set_clk_enet(ENET_125MHz);
}
Hi Joan
set static also not work,and we also cannot get ethernet link today
[ 14.613301] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 14.659308] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 15.137352] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
Thanks
Neil
what bsp version do you use? could you send the whole log file to me? did you change anything in the kernel and uboot?
did you set ipaddr,serverip and netmask in your uboot? if yes, pls send the uboot configuration to me
I didnot set any config in uboot
below is our current uboot config
u-boot=> printenv
baudrate=115200
bootcmd=boota mmc0
bootdelay=1
ethprime=FEC
fastboot_dev=mmc0
fdt_high=0xffffffffffffffff
fdtcontroladdr=b9eece40
idt,prod-id=idt_imx8mq_evt-1_evk_dvt-1
initrd_high=0xffffffffffffffff
loadaddr=0x40480000
soc_type=imx8mq
splashpos=m,m
try to set ipaddr, serverip and netmask in the uboot, try not to conflict with your local ip address
Hello,
1. The Ethernet statistics can provide some good clues. Post the output of:
ethtool -S eth0
We might see RX CRC errors or RX Jabber errors.
You can also confirm 14 packets were transmit as shown in the ifconfig output.
2. You could wireshark the port to see there's egress packets. Knowing if it's an RX only problem or an RX/TX problem is a good clue.
3. Try a 1000Mbps Ethernet connection instead of 100Mbps. Also, it's a good clue if a 1000Mbps connection auto negotiates down to 100Mbps.
4. Probe the PHY registers using mii-tool. Confirm everything looks normal.
how about setting eth0 by yourself, like ifconfig eth0 xx.xx.xx.xx? after you set ip address by yourself, could you ping it?