iMx6, CSI YUV 8 bit, double data rate

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iMx6, CSI YUV 8 bit, double data rate

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alessandroinnoc
Contributor II

Hi !

I am interfacing an ADV7403 device to the iMx6(Dual). This device is very similar to the well known ADV7180, it is much more versatile and accepts several video sources (RGB, CVBS, SVIDEO, etc). Due to the fact we have only a 8 bit CSI port (from CSI_12 to CSI_19) we need to use a video format YUV422 at double data rate, DDR. The LUMA data (8 bits) is sent during the rising edge of the clock, the CHROMA data (4+4 bit) are sent during the falling edge.

So we start from adv7180_tvin driver to create the new one. All it'is working well, but 8 bit DDR video packing doesn't.

We enabled the BT.1120 DDR mode, and the  IPUx_CSI0_SENS_CONF register  is set to 0x00008A42. As result we only get the LUMA but not the CHROMA components. I suppose the CHROMA components are transmitted during the falling edge of the clock.

To test the driver we use the command mxc_v4l2_tvin -ow XXX -oh YYY, on the LCD screen we have a green level image reporting only LUMA. The same is if we use the gstreamer pipeline:

gst-launch tvsrc ! mfw_isink or gst-launch mfw_v4lsrc ! <caps> ! mfw_isink.

Did anybody test the DDR capabilities of iMx6(Dual) ?

Thanks.

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max_tsai
NXP Employee
NXP Employee

hi I think you are talking about data bit depth for YUV or RGB. The physical bus width of BT1120 must be 16-bit or 20-bit.

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mks
Contributor II

Hi,

I have a similar need but with a ADV7181c, I also had a green  level image but still don't know how to fix it...

Could you please tell me if you had a solution to that ?

Thanks.

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max_tsai
NXP Employee
NXP Employee

hi

I didn't test CSI DDR, and your configuration should be fine according to the reference manual.

Can you check if adv7403 outputs progressive 8bit DDR or interleaved 8bit DDR?

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alessandroinnoc
Contributor II

Hi

currently I'm grabbing a SVGA 800x600@60Hz NOT INTERLACED source I realized that ADV7403 cannot interlace and/or de-interlace the processed video, if the video is originally interlaced it is transferred interlaced on its outputs. The same is valid for progressive video.

On ADV7403 clock output I have a 40MHz clock signal, it represents the dot clock of the original SVGA signal and it should be the correct value for a 16 bit wide YUV data and for a 8 bit wide DDR YUV data.

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max_tsai
NXP Employee
NXP Employee

Check CSI0_SENS_PRTCL again, and you are using BT1120 DDR. As I know, BT1120 needs 16-bit bus, but the bus width is 8-bit (CSI_12 to CSI_19). I guess that's the problem.

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alessandroinnoc
Contributor II

Hi

in the (see below) BT.1120 spec is written that the parallel interface can be 8 or 10 bit wide. The bit codes are in the same position as BT.656.

http://www.itu.int/dms_pubrec/itu-r/rec/bt/R-REC-BT.1120-8-201201-I!!PDF-E.pdf

Many Thanks

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max_tsai
NXP Employee
NXP Employee

hi I think you are talking about data bit depth for YUV or RGB. The physical bus width of BT1120 must be 16-bit or 20-bit.

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