iMXRT1175, leakage voltage from USB_VBUS pin

[TCL_1]

Hi,

I have a custom board based on iMXRT1175 processor, it's an USB device board and hot-swap function is required. The problem is I found there is leakage voltage on processor IOs that drain by USB1_VBUS pin, it caused a pulse on processor IOs when hot-swap events happened, and the pulse can reach 1.3V/-0.5V when worst case. See records below. 

My questions are: does these pulses/glitches on IOs when power up are acceptable (I guess no)? how to limit the leakage voltage from USB_VBUS PINs?

Record #1, my custom board. leakage voltage from USB1_VBUS (yellow trace) PIN to processor other IO (blue trace).

Record #2, NXP iMRT117x EVK board, leakage voltage from USB1_VBUS (yellow trace) PIN to processor other IO (blue trace).

Best Regards,

TC Liu

[diego_charles]

Hi @TCL_1 

 It seems that we are seeing the errata ERR010661 from i.MX USB IP. Please provide me time to check this internally, as well your other question below, since  ERR010661 is not listed on RT1170 errata doc.

Snapshot from: https://www.nxp.com/docs/en/errata/IMXRT1060CE_B.pdf

Many thanks for your patience,

Diego

[TCL_1]

Hi,

For iMXRT117x processor USB_VBUS pin, what's the function when the USB controller be used as device, power supply pin or just voltage sense pin?

If it just a voltage sense pin, please review my solution: add ~100K ohm series resistor on USB_VBUS pin to limit the current. and add a divider resistor to make the USB_VBUS pin voltage to keep 4.5V (since the default VBUS valid threshold is 4.4V) when stable, to limit the voltage pulse on VBUS pin.

BR,

TC Liu